EBK ACTIVITIES MANUAL FOR PROGRAMMABLE
EBK ACTIVITIES MANUAL FOR PROGRAMMABLE
5th Edition
ISBN: 8220102795983
Author: Petruzella
Publisher: YUZU
Question
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Chapter 8, Problem 11RQ
Program Plan Intro

a.

Programmable Logic Controller (PLC):

  • Programmable Logic Controller (PLC) is a specialized computer used in industrial segments to control machines and process.
  • PLC is program that consists of a set of instructions which resembles the controlling functions needed to perform specific tasks.
  • The function of PLC is similar to that of a relay and hence, in an industrial segment a relay is greatly replaced by a suitable PLC.
  • When compared to general Personal Computer (PC), a PLC is available in small and tiny sizes.
  • The basic architecture of a PLC consists of an input-output interface module and a small Central Processing Unit (CPU) that runs by control programming language.

PLC counter:

  • A counter is a PLC instruction which counts up or down when the input transfers from an off state (false) to an on state (true).
  • The three different types of counters instructions are as follows:
    • Up counter
    • Down counter
    • Combined counter

Explanation of Solution

b.

Underflow bit of a down-counter:

  • An underflow occurs when the count value goes below its preset value...

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Part A. Combinational Example:1. Practice by entering the following code for a basic two bit comparator circuit and the test benchto test it.2. Execute the code and verify the output.3. Modify the code to add a homework header as well as to create a 3 bit comparator circuit and anappropriate test bench to test it.4. Execute your modified code and verify the output. // Combinational Example is a basic comparator circuit. The output z =1 if x and y are equal. module comparator( input x, input y, output z ); assign z = (~x & ~y) |(x & y); endmodule// testbench for comparator module`timescale 1ns / 1psmodule stimulus;// Inputsreg x;reg y;EGS216 – Lab 8 HDL practice using online Verilog compiler.// Outputswire z;// Instantiate the Unit Under Test (UUT)comparator uut (.x(x),.y(y),.z(z));initial begin // Initialize Inputsx = 0;y = 0;#20 x = 1;#20 y = 1;#20 y = 0;#20 x = 1;#40; endinitial begin$monitor("x=%d,y=%d,z=%d \n",x,y,z);endendmodule
I got 2 inputs and 1 selector bit for A, but dont understand how I would get B or C
3) Write a Verilog code for a 5-bit up/down counter. The counter has reset and enable control signals. module Counter(q_out, d_in, clk, reset, enable, up, down);
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