HW4_Solution

In a certain computer, the virtual addresses are 32 bits long and the physical addresses are 48 bits long. The memory is word addressable. The page size is 16 kB and the word size is 2 bytes. The Translation Look-aside Buffer (TLB) in the address translation path has 64 valid entries. Hit ratio of TLB is 100% then maximum number of distinct virtual addresses that can be translated is K.

The VAX SBI bus uses a distributed, synchronous arbitration scheme. Each SBIN device (i.e., processor, memory, I/O module) has a unique priority and is assigned a unique transfer request (TR) line. The SBI has 16 such lines (TR0, TR1, . . ., TR15), with TR0 having the highest priority. When a device wants to use the bus, it places a reservation for a future time slot by asserting its TR line during the current time slot. At the end of the current time slot, each device with a pending reservation examines the TR lines; the highest-priority device with a reservation uses the next time slot. A maximum of 17 devices can be attached to the bus. The device with priority 16 has no TR line. Why not?

Suppose we have a byte-addressable computer using 2-way set associative mapping with 16-bit main memory addresses and 32 bits, the blocks of cache. Suppose also that each block contains 8 bytes. The size of the block offset field is bits, and the size of the tag field is bits. size of the set field is

6- In 8086Mp bus cycles, the signal (ALE) becomes '1' during clock cycle. 7- The type of the buffer used for buffering data lines is while the type of the buffer used for buffering address lines is 8- During transferring a data of 8-bits from 8086Mp to memory address (1F871H), give the logic value of the following signals: M/IO= RD= = WR= BHE= 9- The benefit of multiplexing operation is 1. CC

(a) Explain the use of TLBs to improve paging efficiency.  (b) Consider a paging system with the page table stored in memory. If a memory reference takes 200 nano seconds, how long does a paged memory reference take? If we add a TLB,  and 75% of all page references are found in the TLB, what is the effective memory reference  time? (Assume that it takes zero time to find an entry in the TLB if it is already present).  (In operating system)

We pointed out that I/O buses do not need separate address lines. Construct a timing diagram similar to Figure 7.11 that describes the handshake between an I/O controller and a disk controller for a write operation. (Hint: You will need to add a control signal.)

Suppose a computer system uses 16-bit addresses for both its virtual and physical addresses. In addition, assume each page (and frame) has size 256 bytes. How many bits are used for the page number? How many bits are used for the offset?  With this system, what’s the maximum number of pages that a process can have?  Suppose that each entry in the page table comprises 4 bytes (including the frame number, the valid bit, and miscellaneous “bookkeeping bits”). An OS uses an array to store the page table. What is the size of the page table?  Furthermore, suppose the first 6 pages of a process map to frames 222 to 227 (as decimal numbers), and the last 5 pages of the process map to frames 1 to 5 (also decimal numbers). All other pages are invalid. Draw the page table, including the valid bit and the frame number.

A cache is set up with a block size of 32 words. There are 16 blocks in cache and set up to be direct map.  You have byte address 0x8923. Show the word address, block address, tag, and index.   Show each access being filled in with a note of hit or miss. You are given word address and the access are: 0xff, 0x08, 0x22, 0x00, 0x39, 0xF3, 0x07, 0xc0

If logical address is (0001100001011) binary find page number p: displacement d:   suppose the page addressed above is stored at frame 7. the physical address for the word addressed above is physical address:   please show and explain all steps

Write an ALP to exchange block of data word by word (8 words) betweentwo memory locations. Assume memory1 address is 6000h and memory2address is 7000h

On a simple paging system with 224 bytes of physical memory, 256 pages of logical address space, and a page size of 210 bytes. 1. How many bits are needed to store an entry in the page table (how wide is the page table)? Assume a valid/invalid 1-bit is included in each entry.    2. If the page table is stored in the main memory with 250nsec access time, how long does a paged memory reference take?  3. If the page table is implemented using associative registers that takes 95nsec. and main memory that takes 200nsec, what is the total access time if 75% of all memory references find their entries in the associative registers?

A processor uses 2-level page tables for virtal to physical address translation. Page tables for hoth levels are stored in the main memory, Virtual and physical addreses are both 12 bits wide. The memory is byte adressable. For virtual to physical address translation, the 10 most significant bits for the virmal address are used as index into the first level poge table while the next 10 bits are used as index into the second level page table. The 12 least significant bits of the virtual address are used as offset within the page. Assume that the page table entries in both levels of page tables are 4 bytes wide. Further, the processor has a translation look-aside a buffer (TLB), with a hit a rate of 96% The TLB caches recently used virtual page numbers and the corresponding physical page numbers The processor also has a physically addressed cache with a hit rate of 90%. Main memory access time is 10 ns, cache access time is 1 ns, and TLB access time is also 10 ns. 26. Assuming that no…

Question 8: A CPU generates 32-bit virtual addresses. The page size is 4 KB. The processor has a translation look-aside buffer (TLB) which can hold a total of 128 page table entries and is 4-way set associative. The minimum size of the TLB tag is: 01 02 0 3 04 1. 11 bits 2. 13 bits 3. 15 bits 4. 20 bits

Consider a system in which bus cycles takes 500 ns. Transfer of bus control in either direction, from processor to I/O device or vice versa, takes 250 ns. One of the I/O de- vices has a data transfer rate of 50 KB/s and employs DMA. Data are transferred one byte at a time. a. Suppose we employ DMA in a burst mode. That is, the DMA interface gains bus mastership prior to the start of a block transfer and maintains control of the bus until the whole block is transferred. For how long would the device tie up the bus when transferring a block of 128 bytes? b. Repeat the calculation for cycle-stealing mode.

(b) Consider a paging system with the page table stored in memory. If a memory referencetakes 200 nano seconds, how long does a paged memory reference take? If we add a TLB,and 75% of all page references are found in the TLB, what is the effective memory referencetime? (Assume that it takes zero time to find an entry in the TLB if it is already present).

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