ESET315_hwk9_due_April19_-_Tagged

Computer Science Please implement Tarry_ST algorithm follow Algorithm on our asynchronous thread simulator - Python Algorithm 4.4 Tarry_ST 1: int parent 2: boolean used[n] + {false} 3: message types token 4: 5: if i = root then > root starts the search send token(i) to any je r(i) used[j] + true, parent ei 8: end if 6: 7: 9: 10: while true do receive token(j) if parent =1 parent +j 11: 12: then > token first time 13: 14: end if if 3j e (r'(i) \parent) :-used[j] then choose an unsearched neighbor parent send token to j used[j]· 15: 16: 17: + true 18: else if i + root then used[parent] + true send token to parent 19: 20: D all neighbors searched 21: 22: end if 23: exit > terminate 24: end if 25: end while

111. distances between nodes in an eight-node network is presented in the from-to distance table below. What is the shortest distance between node 1 to node 8?

60, 1, 100 | 0, 2, 31, 3, 202, 3, 40 | 2, 4, 23, 4, 5 | 3, 5, 54, 5, 9 can you turn the above code into a minimum spanning tree for computer science

What is Minimum Cost Spanning Tree?

Direct Mapping Example: CPU is searching an Instruction stored at RAM address 1110011010 in cache and doesn't find it. What happens then? Tag 0000000000 ?? 0000000001 ?? Block:0, (j=0) 0000000010 Instruction-1 Line1 = 1 Tag Tag 0000000011 Instruction-2 0000000100 Instruction-3 Instruction-4 Block:1, G=1) Solution: 0000000101 Line 2 (= 2) Tag 0000000110 Instruction-5 0000000111 Instruction-6 0000001100 Instruction-7 0000001101 Instruction-8 Block:2 0000001110 Data-1 (j=2) 0000001111 Data-2 Line.3 (3) 0000011100 Data-3 0000011101 Data-4 Tag 0000011110 Data-5 0000011111 Data-6 Cache Size = 64B Size of a line = 4B Total number of Lines in Cache: m 16 RAM Size = 1KB %3D 1111111100 %3D Size of a Block= 4B Total number of Blocks, M = 256 j = 0, 1, 2, ..255 (M-1) Block 255. G =255) 1111111101 1111111110 i = 0, 1, 2, ... 15 (m-1) 1111111111

Solve the following paging address translation Assume the following context of a page directory: Ox0 -> Өx9100B Ox1 -> Өx9100B Ox2 - > Өx291003 Ox3 -> Өx121007 And the following tables: At address Oх91000: -> ӨХЕ4000B Ox1 -> OXF0000B Ox2 -> ӨXF4000B Ox3 -> ӨXF6000B At address Ox291000: Ox0 -> O×4EC000B Ox1 -> Өx4FC000B Ox2 -> O×50C000B Øx3 - > OX51C000B

Create a Code in Python For a node Create a node that creates clusters, the size of the cluster can be any number and it creates a random number of nodes. Each node has a different processing load at the time of the creation of the cluster. Write a pseudo code for the algorithm, where the node selects which data can be processed from the cluster head. Cluster heads can send data any time with any size. The completion time for the data processing task is determined by processing time vs processing load curve.

Operating system

Paging: Select all of the following statements that are true. Systems that use paging but do not support inverted page tables maintain at least one separate page table for each process. The frame table is a system-wide data structure. When paging is applied, the selected page size determines which part of a virtual address belongs to the page number and which to the offset. The page size may differ from the frame size. The Translation Look-aside Buffer (TLB) represents a page directory for all pages in the system. Paging is prone to internal fragmentation.

Glven the below 16-bit Logical Address: 0001000011001101 And the related Process Page Table: Page# Contents 00101 1 00110 01001 3 11001 4 11101 00010 00111 Show the physical address that results from the translation using paging, knowing that the page size is 2K.

Calculate Physical Address of Main memory • Given the contents of CS:IP = [3000H]:[100H] • Given the contents of SS:SP = [50A0H]:[300H] • Given the contents of ES:DI = [60C0H]:[200H] • Given the contents of DS:SI = [A1C0H]:[2F00H] • Given the contents [CS]:[IP]=[1F0AH]:[15A6H] • Given the contents [SS]:[SP]=[82FFH]:[0FA1H]Questions are from Microprocessor (8086)

Distance short 1 to 8. Find min.

Question 8: A CPU generates 32-bit virtual addresses. The page size is 4 KB. The processor has a translation look-aside buffer (TLB) which can hold a total of 128 page table entries and is 4-way set associative. The minimum size of the TLB tag is: 01 02 0 3 04 1. 11 bits 2. 13 bits 3. 15 bits 4. 20 bits

can some one solve this problem by python?

operating systems

What are some of the most frequent computer programs that are used to solve the issue of the least spanning tree?

Consider the block of three-address code                                                          Create DAG (Directed Acyclic Graph) To = a * b T1 = To + j T2 = T0 * T1 T3 = b[T2] j = T3 T4 = j + 2 T5 = c[T4] T6 = a * b * 10 i = T6 sub=i If i <= 15 GOTO (1) note: subject: compailer concepts deptt: cs/It

For a microprocessor the code segment starts at 20000H, and stack segment starts at 21000H.Physical addresses from 21000H to 2FFFFH are accessible from both code and stack segment.These are the physical addresses.● If a location has CS: IP=2000H: 3000H, can we access this location with SS: SP? If yes,what is the SS: SP for this location? If no, why is it not accessible?● If another location has CS: IP=2000H: 0030H, can we access this location with SS: SP? Ifyes, what is the SS: SP for this location? If no, why is it not accessible?

All of the information is below

Computer Science In a data center, Nodes NO...N9 in Rack 1 Nodes N10...N19 in Rack 2 Total nodes N = 20 Student(ld, name, DOB, street, city, district) The tuples are: TO, T1, T2, T3 ....T399 ... ... Id ranges from 202105001 to 202105400 Question 3-1 a.Design a partition vector on Id for storage of student relation b.Find partitions PO, P1, P19

Solve it fast fast plz

Please implement Flood_ST algorithm follow Algorithm on our asynchronous thread simulator. with Python 4.3 Flooding-Based Asynchronous Spanning Tree Construction Algorithm 4.2 Flood_ST 1: int parent +1 2: set of int childs Ø, others Ø 3: message types probe, ack, reject 4: 5: if i = root then > root initiates tree construction 6: send probe to I'(i) 7: parent i 8: end if 9: 10: while (childs U others) + (T(i)\{parent}) do receive msg(j) case msg(j).type of 11: 12: probe: if parent =1 then parent j send ack to j send probe to I(i)\{j} else 13: > probe received first time 14: 15: 16: 17: > probe received before send reject to j childs childs U{j} reject: others + others U{j} 18: D include j in children > include j in unrelated neighbors 19: ack: 20: 21: end while

Data Structure & AlgorithmsExplain an algorithm that can calculate a MAXIMUM SPANNING TREE, and explain how it is different from calculating a MINIMUM SPANNING TREE?

please solve this question (language c/c++)

Computer Science Create a circular link list with at least 7 nodes, and explain in words that how insertion, deletion of a node, and traverse will work. No need for codes and algorithm, just explain in words and design the circular link of 7 nodes.

instruction is in the first picture please give me only implementation of int L1lookup(u_int32_t address) and int L2lookup(u_int32_t address) cacheSim.h #include<stdlib.h>#include<stdio.h>#define DRAM_SIZE 1048576typedef struct cb_struct {unsigned char data[16]; // One cache block is 16 bytes.u_int32_t tag;u_int32_t timeStamp; /// This is used to determine what to evict. You can update the timestamp using cycles.}cacheBlock;typedef struct access {int readWrite; // 0 for read, 1 for writeu_int32_t address;u_int32_t data; // If this is a read access, value here is 0}cacheAccess;// This is our dummy DRAM. You can initialize this in anyway you want to test.unsigned char * DRAM;cacheBlock L1_cache[2][2]; // Our 2-way, 64 byte cachecacheBlock L2_cache[4][4]; // Our 4-way, 256 byte cache// Trace points to a series of cache accesses.FILE *trace;long cycles;void init_DRAM();// This function print the content of the cache in the following format for an N-way cache with M Sets// Set 0…

Describe one of the cache consistency protocols

In MPLAB PIC16F84A Design an algorithm that compares two 3-byte numbers. •Each number is large enough to require 24 bits of 3 bytes of space. (You need 3 addresses for each of them) •There are three possible outcomes (Greater, equal, and lesser). Each outcome leads to a separate subroutine. •Subroutines are not important they can be empty. •Greater Subroutine sets RB0 •Equal Subroutine sets RB1 •Lesser Subroutine sets RB2 Thank you.