HW5

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Computer Science

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Feb 20, 2024

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EECE 7352: Computer Architecture HW5: Due at 11:59pm May 2, 2022 [50 points] As always, goals of these assignments are to help you: (1) practice knowledge gained during the lectures, (2) learn new technical material (esp. experimental learning), (3) apply course concepts and principles to new problems, (4) develop additional skills in expressing yourself in writing and orally, (5) analyze and evaluate ideas, arguments, and points of view. You will not receive any points if you simply copy paste from the suggested readings or online resources. Please express your ideas, understanding and viewpoints in your own words (why steal others’ words to convey what should be completely your point!). Question 1. (5 points) Why do the authors propose to use hashing for inverted page tables in this article “Virtual memory: issues of implementation”? What is the purpose of Hash Anchor Table? https://user.eng.umd.edu/~blj/papers/computer31-6.pdf Question 2. (5 points) Why do the authors of this paper “Effective Mimicry of Belady’s MIN Policy, HPCA’22 (published in February’22)” state that their MockingJay policy is more effective than prior approaches? What is the difference between inferring at priority at the time of insertion vs. at the time eviction? BONUS: if you are able to reproduce their results, please drop me a note (it is not requirement for scoring full points on this question and you don’t need to do it by the deadline). Question 3. (5 points) What is the key idea behind entangled instruction prefetcher (first appeared in the Instruction Prefetching Championship)? https://research.ece.ncsu.edu/wp-content/uploads/sites/19/2020/05/eip_final.pdf https://research.ece.ncsu.edu/ipc/ A more detailed version of this idea later appears in ISCA’21: https://webs.um.es/aros/papers/pdfs/aros- isca21.pdf Hopefully, you will read this version too and benefit from a perspective on the authors’ design choices. Question 4. (10 points) Describe the two TLB prefetchers proposed in the following paper: (1) Leader-Follower, and (2) Distance- based Cross-Core prefetchers. Clearly articulate the motivation and benefits of inter-core TLB prefetching. [ASPLOS 2010] Inter-Core Cooperative TLB Prefetchers for Chip Multiprocessors https://www.cs.yale.edu/homes/abhishek/abhishek-asplos10.pdf
Question 5. (5 points) Assume 40-bit virtual address; 16KB pages; 32-bit physical address; TLB has 8 entries and fully associative; 4 bits are used per TLB and PTE entry for other purposes (dirty bit, valid bit, etc.) Compute the following: (a) The total size (in bits) of TLB. (b) The total size (in bits) of the page table. Question 6. (5 points) A virtual memory system is described by several parameters: N Number of addresses in virtual address space (N = 2 n ) M Number of addresses in physical address space (M = 2 m ) P Page size (P = 2 p ) (in bytes) A virtual address consists of: VPO Virtual page offset (bytes) VPN Virtual page number A physical address consists of: PPO Physical page offset (bytes) PPN Physical page number For a memory system with n = 30 and m = 22, determine the number of bits in the VPN, VPO, PPN, and PPO for the following page sizes: P= 512Bytes, 1KB, and 2KB. Question 7. (5 points) For each configuration (a-c), calculate the number of bits needed for each of the following: • Virtual address • Physical address • Virtual page number • Physical page number • Offset a. 32-bit operating system, 4-KB pages, 1 GB of RAM b. 32-bit operating system, 16-KB pages, 2 GB of RAM c. 64-bit operating system, 16-KB pages, 16 GB of RAM
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