HW1

Computer Organization and ArchitectureAssignment Submit your work by uploading it in Blackboard or bringing it as a hard copy to my office by the deadline. Answer the following question:1-What is the datapath?2-What is the Instruction cycle?3-What is the memory hierarchy? 4-Give small description or example and indicate the format of the following MIPS functions:(The first two of them are examples) Please here is three columns one to instructions and two to format of instruction and three column is to description of function to all instructions but i don't copy to here only  Please solve it. FormatFormatDescription lw $1,100($2)Iload word from $2+100 and put it in $1 and $1,$2,$3Gadd $2 and $3 and put the result in $1 | $1= $2+$3 Sw $1,100($2)   la $1,label   andi $1,$2,100   or $1,$2,100   srl $1,$2,10   li $1,100   move $1,$2   Beq $1,$2,100   Bne $1,$2,100   div $2,$3   Bgt $1,$2,100   addi $1,$2,100   addu $1,$2,$3

Logical address converted into linear address using then into physical address on memory using. A is a logically self-contained unit of code that receives a list of parameters and performs computation, and returns results The combines your program's object file created by the assembler with libraries to produces an executable program makes it possible to start an instruction before completing the execution of previous one. The architecture that has a small and simple instruction set with which all instructions have the same width Uses the system bus to communicate with the processor and to handle low-level operations The mode in which each program can address a maximum of 4 GB of memory. Expensive, used for cache memory, faster access, no refresh The table provided by the operating system contains segment descriptors for all programs and initialized during boot up. A special 32-bit register that indicates the address of the next instruction to be executed by the microprocessor…

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computer architecture Assume that the operation times of one add instruction for the major functional units are 325 ps for memory access, 185 ps for ALU operations and 125 ps for register file read/writes. Please fill the table first and perform the following  a )What is the total cycle in single-cycle implementation?   b )What is the total cycle in pipelining implementation?  c) What is the total cycle in pipelining implementation if there are 5 million add instructions? d) What is the total cycle in pipelining implementation for 5 million add instructions, if the stages are balanced? e)What is the speed up of pipelining implementation over single-cycle implementation?

Q1:.

Assume that the operation times of one add instruction for the major functional units are 325 ps for memory access, 185 ps for ALU operations and 125 ps for register file read/writes. Please fill the table first and perform the following        a )What is the total cycle in single-cycle implementation?   b )What is the total cycle in pipelining implementation?  c) What is the total cycle in pipelining implementation if there are 5 million add instructions? d) What is the total cycle in pipelining implementation for 5 million add instructions, if the stages are balanced? e)What is the speed up of pipelining implementation over single-cycle implementation?

A program runs in 15 seconds on computer X, which has a 2 Ghz clock. You are required to help a computer designer to build another computer, Y, that will run the program in 10 seconds. The designer has determined that a substantial increase in the clock rate is possible, but this increase will affect the rest of the CPU design, causing computer Y to require 1.5 times as many clock cycles as computer for this program. What clock rate should you tell the designer to target? Select one: a.0.3 Ghz b.3 Ghz c.9 Ghz d.8 Ghz

1. Anna designs a 2.5 GHz processor where two important programs, A and B, take onesecond each to execute. Each program has a CPI of 1.25. Elsa is tasked with designingthe company's next-generation processor and she comes up with an idea that improvesthe CPI of A to 1.1 and the CPI of B to 0.9. But the idea is so complex that theprocessor can only be implemented with a cycle time of 0.5 ns. Does Elsa's newprocessor out-perform Anna's processor on program A? How about on program B?2. Consider two different implementations of the same instruction set architecture. Theinstructions can be divided into four classes according to their CPI (class A, B, C, andD). P1 with a clock rate of 2.5 GHz and CPIs of 1, 2, 3, and 3, and P2 with a clockrate of 3 GHz and CPIs of 1, 2, 2, and 2.Given a program with a dynamic instructioncount of 106 instructions divided into classes as follows: 10% class A, 20% class B,50% class C, and 20% class D, which is faster: P1 or P2?

Please written by computer source   Two main techniques are used for memory management in modern computers and operating systems, as described in this module's readings: paging and segmentation. Sometimes they are combined in a segmentation with paging scheme. Design a memory management scheme for a 50 bit computer architecture, using paging, segmentation or both, as described in this module's readings. Your post should include a clear translation scheme from a 50 bit logical address to a 50 bit physical address including a picture that shows how this translation takes place. In particular, each field of the logical address must be clearly depicted and its length in bits must be specified. The proposed scheme must be at least somewhat realistic; for this reason, simple paging and simple segmentation schemes are automatically disqualified, due to the impossible requirements imposed on the implementation in this case (50 bits addresses).

Q6: A digital computer has a memory unit with 24 bits per word. The instruction set consists of 110 different operations. All instructions have an operation code part (opcode) and an address part (allowing for only one address). Each instruction is stored in one word of memory. (a) How many bits are needed for the opcode? (b) How many bits are left for the address part of the instruction? (c) What is the maximum allowable size for memory? (d) Can we extend this instruction set by adding new 10 instructions and keeping the same length of opcode part? (e) Determine the type of this instruction set: stack-based ISA or accumulator- based ISA or general purpose registers-based ISA?

CS & IT Suppose you wish to run a program P with 24.5 x 10 9 instructions on a 8 GHz ww machine with a CPI of 0.60. What is the expected CPU time to execute this program on this machine?

a program runs in 10 seconds on computer A, which has a 4 GHz clock. We are trying to help a computer designer build a computer, B, which will run this program in 6 seconds. The designer has determined that a substantial increase in the clock rate is possible, but this increase will affect the rest of the CPU design, causing computer B to require 1.2 times as many clock cycles as computer A for this program. What clock rate should we tell the designer to target?

Help please mcq

In computer architecture, SIMD may refer to the situation where. a) multiple CPU cores can access the same memory concurrently. b) the same operation can be applied to multiple operands with only a single instruction. c) multiple independent instructions can be executed at the same time in the same CPU core. d) multiple independent memory banks show up as a single address space.

Q2. P1, P2, and P3 are three processors executing the same instruction set. P1 has a 3 GHz clock rate and a Cycle per Instruction (CPI) of 1.5. P2 has a 2.5 GHz clock rate and a CPI of 1.0. P3 has a 4.0 GHz clock rate and has a CPI of 2.2. Based on these values, Answer the following questions (show all calculations and the formulas you are using): 1. Which processor has the highest performance in terms of instructions per second? 2. If the processors individually require 10 seconds to execute a program, find the number of cycles and the number of instructions for each processor. 3. We aim to reduce the execution time by 30% (i.e., in 7 seconds) but this leads to an increase of 20% in the CPI. What clock rates should the processors have to achieve this time reduction?

Please use the photo to answer this question: Compare the cost/performance ratio with and without this improvement.

A two-word directive The address field of LOAD is saved at position 300, and the address field of LOAD is stored at the following location. The address field has a value of 600, and the value saved at 600 is 500, and the value stored at 500 is 650. 400, 401, and 402 are the words stored at 900, 901, and 902, respectively. The number 800 is stored in a processor register R, and the value of the index register is 100. If the instruction's addressing mode is as follows, evaluate the effective address and operand: 1. Immediate 4. Direct 2. Indirect 5. Indirect registration 3. Relationship 6. the index

Sim8085 - A 8085 microprocessor simulator

This is an Operating system review question. Answer the question by true or false. Please help me with this review question, this is not a graded question. please also explain why so that i could understand.

10. The register content for an Intel 8086 microprocessor is as follows:CS = 5000H, DS = 6000H, SS = 7000H, SI = 8000H, DI = 9000HBX = 4A1FH, BP = 3000H, AX = 3597H, CX = 19DAH, DX = 8B73HCalculate the physical address of the memory where the operand is stored and thecontents of the memory locations in each of the addresses shown below:a) MOV [BP + 58], AXb) MOV [SI][BX]+2FH, DXc) MOV [DI][SI]+49AH, DX

introduction to oprating system multichoice questions