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Dec 6, 2023

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ITEC 1000 N Assignment #3 Part A: THE CPU AND MEMORY: 1. If the memory register for a particular computer is 32 bits wide, how much memory can this computer support?  2 32 bytes = 4 Giga Bytes 2. Show the steps of the CPU fetch–execute cycle (micro-operations) for the following instructions in the Little Man instruction set: a. SUBTRACT: i. PC  MAR // Transfer the address from the pc to the MAR ii. MDR  IR // Transfer the instruction to the IR iii. IR [add]  MAR // Address portion of the instruction loaded in MAR iv. A – MDR  A // Contents of MDR subtracted to contents of accumulator v. PC + 1  PC // Program counter incremented b. IN: i. PC  MAR // Transfer the address from the pc to the MAR ii. MDR  IR // Transfer the instruction to the IR iii. IOR  A // Transfer the contents of IOR to the accumulator iv. PC + 1  PC // Program counter incremented

c. COFFEE BREAK: i. PC  MAR // Transfer the address from the pc to the MAR ii. MDR  IR // Transfer the instruction to the IR d. BRANCH ON CONDITION: i. PC  MAR // Transfer the address from the pc to the MAR ii. MDR  IR // Transfer the instruction to the IR iii. A  IOR // Transfer the contents of accumulator to the IOR iv. PC + 1  PC // Program counter incremented 3. Show the steps of the CPU fetch–execute cycle (micro-operations) for an instruction that produces the 2’s complement of the number in accumulator A (calculator): i. PC  MAR // Transfer the address from the pc to the MAR ii. MDR  IR // Transfer the instruction to the IR iii. -A  A // Invert the 0’s and 1’s of the Accumulator A iv. A + 1  A // Accumulator A incremented v. PC + 1  PC // Program counter incremented 4. Assume that SP is the stack pointer regiester, a special purpose register that always refers to the top of the stack. PUSH is an instruction that pushes the address of the next instruction into the top of the stack. Show the steps of the CPU fetch–execute cycle (micro-operations) for the PUSH instruction: i. PC  MAR // Transfer the address from the pc to the MAR ii. MDR  IR, PC + 1  // Decode and increment PC iii. SP  MAR, PC  MDR, SP + 1  SP // Save the PC into the Memory Address that SP is referring to. Increment SP

Part B: CPU AND MEMORY: DESIGN, ENHANCEMENT, AND IMPLEMENTATION: 1. Consider a CPU that implements a single instruction fetch–decode–execute– write–back pipeline for scalar processing. The execution unit of this pipeline assumes that the execution stage requires one step. Describe, and show in diagram form, what happens when an instruction that requires one execution step follows one that requires four execution steps: a. The instruction that requires four execution steps stalls in the pipeline, while the instruction behind it waits for three instruction cycles, creating a three-cycle delay. CPU Clock 0 1 2 3 4 5 6 7 Instruction 1 F D E E E E WB Instruction 2 - F D - - - E WB F: Fetch, D: Decode, E: Execute, WB: Write Back 2. Some systems use a branch prediction method known as static branch prediction, so called because the prediction is made on the basis of the instruction, without regard to history. One possible scenario would have the system predict that all conditional backward branches are taken and all forward conditional branches are not taken. Recall your experience with programming in the Little Man Computer language. Would this algorithm be effective? Why or why not? What aspects of normal programming, in any programming language, support your conclusion :

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