Project_B_Description

B6

draw the curcuit diagram for 4 channel 4 bit multiplexer implemented using 4 channel 1 bit multiplexer. make sure that i need full circuit to save the final multiplexer in the library.

Please may you give the solution to this computer science question! Thank you

3. What is analogue to digital conversion & explain in detail 2-bit quantization.

What’s the difference between sequential and combinational circuits? Also explain what’s the difference between positive and negative edge clock inputs for the flip-clops.

Using 6 NMOS devices, design a NMOS style of the logic gates diagram below. Label the inputs and output.

Include circuit diagram

Write a Verilog code with testbench for 16-bit up/down counter with synchronous reset and synchronous up/down.If up/down is set the counter is up counter and if it is not set, the counter is a down counter.     submit the module code, testbench code, and the simulation results. PLEASE EXECUTE CODE IN VERILOG

Consider the following schematic diagram: If R1 = 10 kO, and R2 = 10 kO, this circuit would be that of: Select one: O a. A non-inverting amplifier O b. A buffer C. An inverter Activate Wind Go to Senings to O d. An inverting summer

Q1. (a) Design a stick (layout) diagram for the following static CMOS logic gate, where A, B, C, D are the logic gate inputs and O/P is the output: VDD D-d[Q8 A-Q5 B-Q6 C-d [Q7 O/P CQ3 DQ4 B-Q2 AQ1 Vss Figure 1 Use dual-well, CMOS technology. Include wells, well-taps, contact cuts, routing of power and GND in your diagram. Use colour coding and/or clear and readable detailed annotations to represent the wires in the different layers. (b) The logic gate from (a) needs to drive a capacitive load of 150 fF with a rise-time and fall-time of 1.2 ns. If the length of all transistors is 0.5 μm, calculate the required widths for all P-type and all N-type MOSFETs in the logic gate to achieve the required edge-speeds. Clearly show the calculation steps of your solution. Assume VDD = 5 V, K'n = 50 μA/V², K'p = 20 μA/V²

Q1. (a) Design a stick (layout) diagram for the following static CMOS logic gate, where A, B, C, D are the logic gate inputs and O/P is the output: VDD D-d[Q8 A-Q5 B-Q6 c-d[Q7 O/P CQ3 DQ4 B-Q2 A-Q1 Vss Figure 1 Use dual-well, CMOS technology. Include wells, well-taps, contact cuts, routing of power and GND in your diagram. Use colour coding and/or clear and readable detailed annotations to represent the wires in the different layers.

A certain digital circuits designed to operate with voltage levels of -0.2Vdc and -3.0Vdc. If H= 1 =-0.2 Vdc and L =0 =-3.0 Vdc, is this positive logic or negative logic ? H=+5.0Vdc. and. L=+1.0Vdc What are the voltage levels between fall and rise times are measured? What is the value of Duty cycle H if the waveform is high for 2 ms and low for 5 ms?

An Intel 8085 processor is executing the program given below. MVI A, 10H MVI B, 10H BACK NOP : ADD B RLC JNC BACK HLT The number of times that the operation NOP will be executed is equal to

Q1// What are the difference between Logic Devices and Programmable Logic Devices? Q2// Explain the advantage's of Programmable Logic Devices? Q3// List the disadvantages of Fixed function logic devices. Q4// Compare between Logic Devices and Programmable Logic Devices?

Can I get the written solution by hand and not ai

3b will upvote for correct answers

what is the principle of the of the single arm bridge strain gauge Describe the pin connection and communication principle between devices or MCU by Uart bus

Q2. (a) Figure 2 shows the pinout diagram (and their functional description) of the 2114 Static RAM memory IC. Using a neat sketch show how such IC may be interfaced with an M68000 microprocessor to realise a system that needs 1K x 16 bits of RAM. [Note: 2114 is a 4-bit memory IC. You will need multiple ICs to make up the 16-bit address bus of M68000 processor.] Ao-Ag Pin Names Address Inputs A6 1 A5 2 A4 AO 5 A16 A2 7 CS 8 GND 9 -23456782 18 Vcc WE Write Enable 17 A7 CS Chip Select 16 A8 1/0₁-1/04 Data Input/Output A3 4 15 A9 VCC Power (+5V) GND Ground 14 I/O 1 13 I/O 2 Truth Table 12 1/03 CS WE Comments 11 I/O 4 H X Chip Deselected L L Write 10 WE L H Read Figure 2 (b) Design an address decoder circuit to realise the following memory map (shown below in hexadecimal notation). The unused address range should generate an active low signal to be connected to the BERR* input of the M68000 microprocessor. Use the partial address decoding technique for your design. ROM1 00 0000 03 FFFF…

Q2. (a) Figure 2 shows the pinout diagram (and their functional description) of the 2114 Static RAM memory IC. Using a neat sketch show how such IC may be interfaced with an M68000 microprocessor to realise a system that needs 1K x 16 bits of RAM. [Note: 2114 is a 4-bit memory IC. You will need multiple ICs to make up the 16-bit address bus of M68000 processor.] Ao-Ag Pin Names Address Inputs A6 1 A5 2 A4 3 A3 4 AO 5 A1 6 A2 7 CS 8 GND 9 +23456700 18 Vcc WE Write Enable 17 A7 CS Chip Select 16 A8 1/01-1/04 Data Input/Output 15 A9 Vcc Power (+5V) GND Ground 14 I/O 1 13 I/O 2 Truth Table 12 1/03 CS WE Comments 11 1/04 Н Chip Deselected L L Write 10 WE L H Read Figure 2 (b) Design an address decoder circuit to realise the following memory map (shown below in hexadecimal notation). The unused address range should generate an active low signal to be connected to the BERR* input of the M68000 microprocessor. Use the partial address decoding technique for your design. ROM1 00 0000 03 FFFF…

Draw the circuit diagram of 4-bit Ripple Carry Adder. Page 6 of 8

Please do part b using the Assumption

Draw the logic diagram and transistor implementation for a (2-2-2) AOI.

Determine at least three contemporary tools that may aid in the design of digital logic circuits. Identify and discuss the tools' five most important characteristics. Propose the best option for logic circuit design (justify your selection)

(c) Identify and draw the simplified logic circuit for Figure Q5(c) by using only a single (1) logic gate that can be applied to replace the whole circuit. Figure Q5(c) X

Please may you give the solution to this computer science question in a step by step form. Thank you

I need an expert's solution for using the (emu8086)  program.

Q1) For the circuits shown in figures 1 and 2: 1. What is the function of output? 2. Find the max. and min. Vol. value? 3. Determine the static power (avg.)? 4. Design equivalent logic circuit by CMOC logic circuits? Use VDD= 10 V. Vr.o=1V. Vru-1V. (W/L)o= (5/2), (W/L)L (20/2), RD = 40k, KL = 10P A/V^2 and KO = 40pA/V`2? Figure 1 5 VDD RD Figure 2 बदना दे

Q2: Explain the role of Stack Register in 8086 Microprocessor.