Test2_2200v4_solutions

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Auburn University *

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2200

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Electrical Engineering

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Apr 3, 2024

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ELEC 2200-005, Test 2 s 1 of 9 Total 70 points ELEC 2200 Digital Logic Circuits Class Test 2, Broun 102, 2:00-2:50PM Instructions: You must answer a total of 7 of the following 16 problems. You may want to read the problems in each section before starting. All problems are worth the same number of points. Place a check mark on the line to the right of the problems you would like graded. Thank you and good luck! Section A: Complete 2 of the following 6 problems Problem 1: _____ Minimize the Boolean equation f(A,B,C,D) = A + (B’ + C)( BC’ + D’), Problem 2: _____ Implement the function from Problem 1 using only a minimum number of NAND gates (except for any required inverters). Foil the binomials: f = A + B'BC' + B'D' + CBC' + C'D' = A + 0 + B'D' + 0 + C'D' = A + B'D' + C'D' Start with AND-OR circuit. Convert to NAND-NAND (OR with all inputs inverted is equivalent to NAND)
ELEC 2200-005, , Test 2 s 2 of 9 Problem 3: _____ Minimize the Boolean equation f(A,B,C,D) = (A’ + B’ + D’) (A + B’ + C’) (A’ + B + D’) (B + C’ + D’) Problem 4: _____ Implement the function from Problem 3 using only a minimum number of NOR gates (except for any required inverters). Start with OR-AND circuit. Convert to NOR-NOR (AND with all inputs inverted is equivalent to NOR) f(A,B,C,D) =
ELEC 2200-005, , Test 2 s 3 of 9 Problem 5: _____ A sequence of inputs is applied to the circuit below, generating the accompanying timing diagram. Assume that each gate has a propagation delay of 1 time unit (TPD). Find the minimized logic expression for the circuit, the truth table for the circuit, and the maximum propagation delay ( show your work for full credit ). Note that new inputs are applied at time t1, t2, … etc. Output f(A,B,C) changes at time t1 + 2, t4 + 3, t7 + 3, etc. Largest delay is 3 after new inputs are applied at times t4 and t7.
ELEC 2200-005, , Test 2 s 4 of 9 Problem 6: _____ Consider the Boolean logic function f(x,y,z) = Σ m (0, 2, 4, 5). (a) Draw the circuit schematic for the function above using a minimum number of (b) Draw the timing diagram for the circuit assuming a zero propagation delay. (c) Write either a VHDL or Verilog structural implementation for the circuit with each gate implementing a propagation delay of 1 ns. AND and OR gates. Verilog module part_c (f,x,y,z); input x,y,z; output f; wire s,t; and #1 (s,~x,~z); and #1 (t,x,~y); or #1 (f,s,t); endmodule VHDL entity part_c is port(x,y,z: in std_logic; f: out std_logic); end part_c; architecture of part_c is signal s,t: std_logic; begin s <= not x and not z after 1 ns; t <= x and not y after 1 ns; f <= s or t after 1ns; end
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