1. What is the difference (or differences) between a TLB and on-chip cache? a. The TLB is direct-mapped, while caches are set associative. b. The TLB is indexed by the virtual address, while caches are Indexed by the physical address. c. The TLB stores virtual-to-physical address transiations, while caches store data. d. The TLB can be slow, but caches need to be fast. e. The TLB stores instructions, while caches store data. 2. Say we have two mutexes, implemented with binary semaphores, and two threads which access them. Which of the following can cause deadlock. a. The threads lock the mutexes in the same order. b. The threads lock the mutexes in a different order. C. The threads unlock the mutexes in the same order. d. The threads uniock the mutexes in a different order.

1. What is the difference (or differences) between a TLB and on-chip cache? a. The TLB is direct-mapped, while caches are set associative. b. The TLB is indexed by the virtual address, while caches are Indexed by the physical address. c. The TLB stores virtual-to-physical address transiations, while caches store data. d. The TLB can be slow, but caches need to be fast. e. The TLB stores instructions, while caches store data. 2. Say we have two mutexes, implemented with binary semaphores, and two threads which access them. Which of the following can cause deadlock. a. The threads lock the mutexes in the same order. b. The threads lock the mutexes in a different order. C. The threads unlock the mutexes in the same order. d. The threads uniock the mutexes in a different order.

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Question 1 Consider a memory system that uses a 32-bit address at the byte level, plus a cache that uses a 64-byte line size. a)Assume a direct mapped cache with a tag field in the address of 20 bits. Show the address format and determine the following parameters: number of addressable units, number of blocks in main memory, number of lines in cache, size of tag b) Assume an associative cache. Show the address format and determine the following parameters: number of addressable units, number of blocks in main memory, number of lines in cache, size of tag. c) Assume a four-way set-associative cache with a tag field in the address of 9 bits. Show the address format and determine the following parameters: number of addressable units, number of blocks in main memory, number of lines in set, number of sets in cache, number of lines in cache, size of tag.
Suppose a byte-addressable computer using set associative cache has 224 bytes of main memory and a cache size of 64K bytes, and each cache block contains 32 bytes. a) If this cache is 2-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and offset fields? b) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache?
For a computer with 56-bit physical addresses and a 8-way set associative cache of 64 KB where each cache line has the capacity of holding 32 words. Assume the word size is 3 and the architecture is byte-addressable. Answer the questions below: a.How many bits are needed for tag, index, word offset, and byte offs. Show your derivations and assumptions. b.What are the start and end physical addresses, in hex as discussed in class, for cache line 300? Cache line count starts from 0. c.What is the total size, in KB, of this cache? d.What is the tag value, in hex, of address 0xABCDEF98765432?
1. For a direct-mapped cache design with a 32-bit address, the following bits of address are used to access the cache. Tag Index Offset 31-14 13-7 6-0 a. What is the cache block size (in words)? b. How many entries does this cache have? c. What is the ratio between total bits required for such a cache implementation over the data storage bits?
2. Consider a computer with the following characteristics: total of 1Mbyte of main memory; Content of each addressable location is 1 byte; block size of 16 bytes; and cache size of 64 Kbytes. (a) For the main memory addresses of F0010, 01234, and CABBE, give the corresponding tag, cache line address, and word offsets for a direct-mapped cache. (b) Give any two main memory addresses with different tags that map to the same cache slot for a direct-mapped cache. (c) For the main memory addresses of F0010 and CABBE, give the corresponding tag and offset values for a fully-associative cache. (d) For the main memory addresses of F0010 and CABBE, give the corresponding tag, cache set, and offset values for a two-way set-associative cache.
Suppose a byte-addressable computer using set associative cache has 4Mbyes of main memory and a cache of 64 blocks, where each cache block contains 8 bytes. a) If this cache is 2-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and offset fields? b) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache? Show all work and explain how you got the answers please. Thanks
Suppose a computer using direct mapped cache has 4M byte of byte-addressable main memory, and a cache of 512 blocks, where each cache block contains 64 bytes. a) How many blocks of main memory are there? b) What is the format of a memory address as seen by the cache, i.e., what are the sizes of the tag, block, and offset fields? c) To which cache block will the memory address 0x00007266 map?
Suppose a byte-addressable computer using set associative cache has 216 bytes of main memory and a cache of 32 blocks, and each cache block contains 8 bytes. a) If this cache is 2-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and offset fields? b) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache?
Let's pretend for a moment that we had a byte-addressable computer with 2-way set associative mapping, 16-bit main memory addresses, and 32 cache memory blocks at our disposal. Using the information that there are 8 bytes in each block, calculate the size of the offset field and show your results.
Suppose a computer using direct mapped cache has 4G Bytes of main memory and a cache of 256 Blocks, where each cache Block has 16 Words, and Word Size is 4 Bytes. a)How many blocks of main memory? b)What is the format of a memory address as seen by the cache (Tag, Block and Word fields)? c)To which cache block will the memory reference 0000146A in Hex?
Consider the following situation: we have a byte-addressable computer with 2-way set associative mapping, 16-bit main memory addresses, and 32 blocks of cache memory. Based on the fact that each block has 8 bytes, figure out how big the offset field should be, and then show your work.
Consider a 128-word L2 memory and a 16-word direct mapped L1 cache.a. How many bits are in the address of the L2 memory?b. How many index bits are in the L1 address?c. How many tag bits are in the L1 address?d. How many words from the L2 memory will map to the same word in L1?