2. Generate 4x2 Priority encoder truth table and draw logic circuit diagram and schematic. Construct and verify if the circuit prioritizes the highest input only. (You must not use the standard priority encoder ICs included in Circuit Verse)

4. CMOS Logic Gate The PUN of a CMOS Logic Gate is shown below Vdd Q1 B- Q2 c -dPQ3 B-dCa5 Q6 D Y (a) Determine Y from the PUN. Express your answer in Sum-of-Product form. (b) Sketch the PDN of this CMOS logic gate. (c) Transistor sizing. If we set Peg = 5 for this CMOS logic gate, find W's for Q1 through Q7 if L is set at 0.25µm.

Please do part b using the Assumption

What are some applications for the logic synthesis tool?