Answered: a) How large must the mode field be?…

Name: The memory unit of a computer has 1M words of 32 bits each. The comput
Uploaded: 2024-03-20T06:51:23.000Z
Channel: Bartleby
Description: The memory unit of a computer has 1M words of 32 bits each. The computer has aninstruction format with 4 fields: an opcode field; a mode field to specify 1 of 6 addressingmodes; a register address field to specify one of 28 registers; and a memory ad

Engineering

Computer Science

a) How large must the mode field be? b) How large must the register field be? c) How large must the address field be? d) How large is the opcode field?

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 2PE: If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the...

See similar textbooks

Similar questions

Consider a Computer which has a memory which is capable of storing 4096 K words and each word in memory can be of size 32 bits. The computer supports a total of 6 addressingmodes, and it has 60 computer registers. The computer supports instructions, where each instruction consists of following fields: Mode Operation code Register Register Memory AddressGiven that each instruction will be stored in one memory word, discuss with a suitable diagram the format of instruction by specifying number of bits for each field of instruction. Discuss each field of instruction.
Consider a computer which has a memory which is capable of storing 4096 K words and each word in memory can be of size 32 bits. The computer supports a total of “8” addressing modes, and it has “50” computer registers. The computer supports instructions, where each instruction consists of following fields: Mode Operation code Register Register Memory Address Given that each instruction will be stored in one memory word, discuss with a suitable diagram the format of instruction by specifying number of bits for each field of instruction. Discuss each field of instruction
Consider memory storage of a 32-bit word stored at memory word 34 in a byte addressable memory. (a) What is the byte address of memory word 34? (b) What are the byte addresses that memory word 34 spans? (c) Draw the number 0x3F526372 stored at word 342 in both big-endian and little-endian machines. Clearly label the byte address corresponding to each data byte value.
I want all steps for Consider a computer which has a memory which is capable of storing 4096 K words and each word in memory can be of size 32 bits. The computer supports a total of “6” addressing modes, and it has “7” computer registers. The computer supports instructions, where each instruction consists of following fields: • Mode • Operation code • Register • Register • Memory Address Given that each instruction will be stored in one memory word, discuss with a suitable diagram the format of instruction by specifying number of bits for each field of instruction. Discuss each field of instruction
the available space list of a computer memory is specified as follows: 9 start address block address in words 100 50 200 150 450 600 1200 400 determine the available space list after allocating the space for the stream of requests consisting of the following block sizes: 25,100,250,200,100,150 use i) first fit ii) best fit and iii) worst fit algorithms
Two main techniques are used for memory management in modern computers and operating systems, as described in this module's readings: paging and segmentation. Sometimes they are combined in a segmentation with paging scheme. Design a memory management scheme for a 50 bit computer architecture, using paging, segmentation or both, as described in this module's readings. Your post should include a clear translation scheme from a 50 bit logical address to a 50 bit physical address including a picture that shows how this translation takes place. In particular, each field of the logical address must be clearly depicted and its length in bits must be specified. The proposed scheme must be at least somewhat realistic; for this reason, simple paging and simple segmentation schemes are automatically disqualified, due to the impossible requirements imposed on the implementation in this case (50 bits addresses)
Assume a CPU with a fixed 32-bit instruction length has the following instruction format:opcode mode [operand1] [operand2] [operand3]The mode encodes the number of operands and each operand’s mode. For instance, one mode indicates three registers, another indicates two registers and an immediate datum, another indicates a main memory reference, etc. Assume there are 94 instructions and 22 modes. Answer the following.a. One mode indicates three registers. How many registers can be referenced in this mode?b. One mode indicates two registers and an immediate datum in two’s complement. Assuming there are 32 registers, what is the largest immediate datum that can be referenced?c. One mode has a destination register and a source memory address (an unsignednumber). Assuming 16 registers, what is the largest memory reference available?d. One mode has two memory addresses, both using base displacement. In both, the basesare stored in index registers and the displacements are specified in the…
Suppose a computer using fully associative cache has 4 Gbytes of byte-addressable main memory and a cache of 256 blocks, where each cache block contains 32 bytes. a) How many blocks of main memory are there? b) What is the format of a memory address? Provide the names and the sizes of the fields. c) To which cache block will the memory address 0x01752 map?
Suppose a program’s 15-th logical instruction (counting starts from zeroth) is at physical address 1234ABDE16 in the RAM. (contents of any logical address fits into any physical address) What is the physical address in the RAM where the program has been loaded? What is the physical address in the RAM of the last instruction of the program if it has 37 logical instructions altogether?
Q1: Suppose the hypothetical processor has two I/O instructions: (3+3+3)0011=Load AC from I/O0111=Store AC to I/OIn this case, the 12-bit address identifies a particular external device. Show the program execution using figure for the following program:a) Load AC from device 6b) Add contents of memory location 880c) Store AC to device 7 (Note: Question is to be solved similar to the pictures attached with minimum explaination of a line or two with the steps and SHOULD include the memory location 880 as stated in the question)
Suppose that each of the 4 processors in a shared memory multi-processor system is rated at 400 MIPS. A program contains a purely sequential part that accounts for 22% of the program’s execution time on a single processor. The remaining code can be partitioned into three independent parts (A, B, and C). Running on a single processor, part A accounts for 30% of the program’s execution time, part B accounts for 18%, and part C accounts for 30%. What is the apparent MIPS rating for the program if it is run on the 4-processor system and the sequential part must be completed before any of the remaining independent parts (A, B or C) can run in parallel?
QUESTION 2 Discuss with examples the main difference between system programming and application programming and explain in your own words how each of these can be carried out in the computer system. With your knowledge in memory addressing modes and using the given opcodes LDA = 00 0000 0000 (00) 0 (x) What will be the content of the address loaded into the accumulator? b. With your knowledge in memory addressing mods and using the given opcodes STCH = OX54 Buffer = 1000 0101 0100 (00) 1 (x) 000 1000 0000 0000 () 011 0000 0000 0000 () What will be target address? Briefly explain the usage of the JSUB and RSUB instruction sets in an SIC architecture coding