Consider a 32-bit computer using byte-addressable memory accessing different types of cache. Each cache consists of 256 blocks with one 32-bit word per block.  Specify how many bits are used for the tag, index or set, and byte offset for each type of cache listed in the table

Problem 0. The following table gives some of the parameters for a number of different hardware caches. Fill in the table with the values of the missing parameters. Recall that m is the number of physical address bits, C is the cache size in bytes, B is the block size in bytes, E is the associativity, i.e., lines per set, S is the number of sets, t is the number of tag bits, s is the number of set index bits, and b is the number of block offset bits. Cache m 48 32030 (b) 48 32 24 24 C B E 16384 32 16 32768 64 65536 128 512 32 1024 8 8 4 14 1 4 S b S t

HELP WITH PART A,B, AND C

The phrases "unified cache" and "Hadley cache" should be defined.