Consider the 2-address instruction SUBR1, X which subtract the contents of location X from the contents of register R1 and places the result in R1. The ALU can complement either of its inputs, but it cannot subtract. Integers are stored in two's complement representation. List the sequence of micro-operationsto implement the instruction. Assume processor registers PC, MAR, MBR, IR with their usual meanings.

Consider the 2-address instruction SUBR1, X which subtract the contents of location X from the contents of register R1 and places the result in R1. The ALU can complement either of its inputs, but it cannot subtract. Integers are stored in two's complement representation. List the sequence of micro-operationsto implement the instruction. Assume processor registers PC, MAR, MBR, IR with their usual meanings.

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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17. Consider the following hypothetical instruction: SubMem R1, mem1, mem2 This instruction works as follows: \[ \mathrm{R} 1 \leftarrow \text { [mem1] - [mem2] } \] In a multi-cycle datapath implementation, this instruction will: a. Use the MDR twice b. Use the ALU once c. Use the "shift to left" unit twice d. None of the above Answer: B 18. Consider the following hypothetical instruction: Mems mem1, R1, mem2 This instruction works as follows: \[ \text { [mem1] } \leftarrow \mathrm{R} 1 \text { - [mem2] } \] One of the following is correct about this instruction: a. It will not need theBregister b. It will require priting into MDR twice c. It will require writing into the ALUout three times d. None of the above Answer: A 19. By comparing the hypothetical instructions given in Questions (17) and (18), if we run these instructions on the same processor, then one of the following is correct: a. Both instructions have the same CPI b. Mems executes faster than SubMem c. SubMem executes…
In this exercise, we examine in detail how much an instruction is executed in a single-cycle Datapath. The problem refers to a clock cycle in which the processor fetches the following instruction word: 1010 1100 0110 0010 0000 0000 0001 0100. Assume that data memory is all zeros and that the processor's registers have the following values at the beginning of the cycle in which of the instruction word is fetched: (See image attached) What is the new PC address after this instruction is executed? Highlight the path through which this value is determined?
5. Consider the 2-address instruction SUB R1, X which subtract the contents of location X from the contents of register R1 and places the result in R1. The ALU can complement either of its inputs, but it cannot subtract. Integers are stored in two’s complement representation.List the sequence of micro-operations to implement the instruction. Assume processor registers PC, MAR, MBR, IR with their usual meanings
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Consider a HW ISA program P1 with the following Instruction Memory IM: Jamie wants to translate program P1 (except for the final HALT instruction) into a sequence of statements in a version of C with a 16-bit int type. Using the IM Fill in the rest of her program with assignments to variables named R2, R3, and R4 that represent the registers with these names in P1 and a while loop. int R0 = 0; int R1 = 1; int R2 = R0 + R0; // ...
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In this exercise we compare the performance of 1-issue and 2-issue processors, taking into account program transformations that can be made to optimize for 2-issue execution. Problems in this exercise refer to the following loop(written in C):for(i=0;i!=j;i+=2)b[i]=a[i]–a[i+1];When writing MIPS code, assume that variables are kept in registers as follows, and that all registers except those indicated as Free are used to keep various variables, so they cannot be used for anything else. i j a b c Free R5 R6 R1 R2 R3 R10,R11,R12 Translate this C code into MIPS instructions. Your translation should be direct, without rearranging instructions to achieve better performance.
Considering the following contents of Stack Segment (SS) Register and Stack Pointer (SP) Register: SS = A5B0H, SP = 4DF0H (a) Calculate the values of Top of Stack (ToS) and Bottom of Stack (BoS)? (b) Consider the following operations on the stack: PUSH AX PUSH [CX] PUSH 10 POP [BX] POP AX What is the value of ToS after all these operations? Also, provide the value of ToS after each instruction.
A 32-bit computer has 32 registers, and a memory addressed by bytes with two cycles for reading and writing operations. Consider the instruction ADD, R1, addr. This instruction adds the value stored in R1 to the value stored in the memory address addr, and stores the result in the register R1. a) Show a possible format for this instruction, having into account that the computer has 100 machine instructions and the addresses are represented using 32 bits. b) Indicate the elemental operations and control signals needed to execute the previous instruction.
We will explore the impact of cache capacity on performance, focusing exclusively on the data cache and excluding instruction storage in the caches. Cache access time is directly linked to its capacity. For the sake of simplicity, let's assume that accessing the main memory takes 100ns, and in a specific program, 50% of instructions involve data access. Two distinct processors, denoted as P1 and P2, are engaged in executing this program. Each processor is equipped with its own L1 cache. L1 size L1 Miss Rate L1 Hit Time P1 64 KB 3.6% 1.26 ns P2 128 KB 3.1% 2.17ns (a) What is the AMAT for P1 and P2 assuming no other levels of cache?
Very urgently needed!! Suppose before the CALL instruction within a code the registers hasfollowing data:SS=1E00H, SP=000AH, CS=85D9H, IP=10B5H, AX =1D02H, CX=04A8Hand DX=6550H.Draw a schematic diagram to illustrate what will happen after the CALLinstruction executes. Note that CALL instruction also stores the value ofregisters AX, DX and CX into the stack segment as they are being used inthe called procedure.