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Consider the delays given in the table below. Ted Cruz builds a prefix adder that reduces the ALU delay by 50 ps. If the other element delays stay the same, find the new cycle time of the single-cycle MIPS processor and determine how long it takes to execute a benchmark with 100 billion instructions. Instruction [25-0] Jump address (31-0] Shift left 2 26 28 PC + 4 [31-28) Add ALU Add resut Shift left 2 RegDst Jump Branch MemRead MemtoReg ALUOP MemWrite ALUSrc RegWrite Instruction (31-26 Control instruction [25-21] Read Read address register 1 Read PC Instruction [20-16] data 1 Read register 2 Zero Instruction (31-0) InstructionInstruction (15-11 ALU ALU Write register Read data 2 Address Read data result memory Write data Registers Data Write data memory Instruction [15-0] 16 32 Sign- extend ALU control Instruction [5-0) Assume: memory units (read or write): 250 ps ALU and adders: 200 ps register file (read or write): 50 ps other combinational logic: 25 ps

Consider the delays given in the table below. Ted Cruz builds a prefix adder that reduces the ALU delay by 50 ps. If the other element delays stay the same, find the new cycle time of the single-cycle MIPS processor and determine how long it takes to execute a benchmark with 100 billion instructions. Instruction [25-0] Jump address (31-0] Shift left 2 26 28 PC + 4 [31-28) Add ALU Add resut Shift left 2 RegDst Jump Branch MemRead MemtoReg ALUOP MemWrite ALUSrc RegWrite Instruction (31-26 Control instruction [25-21] Read Read address register 1 Read PC Instruction [20-16] data 1 Read register 2 Zero Instruction (31-0) InstructionInstruction (15-11 ALU ALU Write register Read data 2 Address Read data result memory Write data Registers Data Write data memory Instruction [15-0] 16 32 Sign- extend ALU control Instruction [5-0) Assume: memory units (read or write): 250 ps ALU and adders: 200 ps register file (read or write): 50 ps other combinational logic: 25 ps

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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Consider the delays given in the table below. Ted Cruz builds a prefix adder that reduces the ALU delay by 50 ps. If the other element delays stay the same, find the new cycle time of the single-cycle MIPS processor and determine how long it takes to execute a benchmark with 100 billion instructions. Instruction [25-0] Shift Jump address [31-0] 26 left 2 28 |PC + 4 [31-28) Add ALU Add result Shift left 2 RegDst Jump Branch MemRead MemtoReg ALUOP MemWrite ALUSrc RegWrite Instruction (31-26) Control instruction [25-21) Read PC Read address register 1 Read instruction [20-16] data 1 Read register 2 Zero Instruction (31-0) Instruction Instruction [15-11l register data 2 ALU ALU Read Read Write Address result data memory Write data Registers Data Write data memory Instruction [15-0] 16 32 Sign- ALU extend control Instruction [5-0) Assume: memory units (read or write): 250 ps ALU and adders: 200 ps register file (read or write): 50 ps other combinational logic: 25 ps
Transcribed Image Text:Consider the delays given in the table below. Ted Cruz builds a prefix adder that reduces the ALU delay by 50 ps. If the other element delays stay the same, find the new cycle time of the single-cycle MIPS processor and determine how long it takes to execute a benchmark with 100 billion instructions. Instruction [25-0] Shift Jump address [31-0] 26 left 2 28 |PC + 4 [31-28) Add ALU Add result Shift left 2 RegDst Jump Branch MemRead MemtoReg ALUOP MemWrite ALUSrc RegWrite Instruction (31-26) Control instruction [25-21) Read PC Read address register 1 Read instruction [20-16] data 1 Read register 2 Zero Instruction (31-0) Instruction Instruction [15-11l register data 2 ALU ALU Read Read Write Address result data memory Write data Registers Data Write data memory Instruction [15-0] 16 32 Sign- ALU extend control Instruction [5-0) Assume: memory units (read or write): 250 ps ALU and adders: 200 ps register file (read or write): 50 ps other combinational logic: 25 ps
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