Construct a timing diagram showing input and output waveforms for the case where the BCD inputs sequence through the decimal numbers as follows: 0, 2, 4, 6, 8, 1, 3, 5, and 9.

H.W :- 1) A four logic-signal A,B,C,D are being used to represent a 4-bit binary number with A as the LSB and D as the MSB. The binary inputs are fed to a logic circuit that produces a logic 1 (HIGH) output only when the binary number is greater than 01102-610. Design this circuit. 2) repeat problem 1 for the output will be 0 (LOW) when the binary input is less than 01112-710- Saleem Lateef

Develop the Q output waveforms for a 74HC190 up/down counter with the input waveforms shown in figure below. A binary 0 is on the data inputs. Start with a count of 0000. CLK CTEN LOAD

Problem #3 The input waveforms shown below are applied to a 2-bit adder. Draw the timing diagram for the sum and the output carry.

A 9-bit asynchronous counter has a 128-kHz clock signal applied. (1) What is the MOD number of this counter? MOD number = (ii) What will be the frequency at the MSB output? fmsb = (iii) Assume that the counter starts at zero. What will be the count after 635 input pulses? After 635 input pulse, Count =

Design a combinational circuit that takes 3-bit pattern as input and outputs binary code of bit position of the first 1' in the pattern reading from MSB (2nd position) to LSB (0th position).An additional output variable V is required along with binary code to indicate that the binary code is valid or note i.e., if the input pattern is '000' then the output V should be '0' to indicate that the binary code is not indicating the bit position of first 1' and we don't care about the binary code if V = 0. Design the required circuit using dual 4x1 MUXS and minimum additional logic.Available resources along with dual 4x1 MUXS are NOT gates, 2-input(AND, OR, NAND, NOR) gates.

c. Sketch the zero-pole plot and the direct form II diagram of the completed design out of part b. d. Calculate and sketch the output sequence after feeding x [n] into this system.

The error detector compares the ....to the and .. .. produces an error signal equal to the difference between the two. setpoint/desired output measured output/actual output desired output/measured output Set point/Measured output

Design a combinational circuit with the four inputs A,B.C, and D, and three outputs X, Y, and Z. When the binary input is odd number, the binary output is one lesser than the input. When the binary input is even number the binary output is one greate than the input. Implement the function using multiplexers with minimal input and select line.

The clock source generates a frequency PCLK = 80 MHz and scaling factor 4. The maximum counting time is 300 seconds. Find the DC and the frequency. How many events do we count and what register is used to store them.