Design a combinational circuit that takes 3-bit pattern as input and outputs binary code of bit position of the first ʻ1’ in the pattern reading from MSB (2nd position) to LSB (0th position).An additional output variable V is required along with binary code to indicate that the binary code is valid or note i.e., if the input pattern is '000' then the output V should be '0' to indicate that the binary code is not indicating the bit position of first 1' and we don't care about the binary code if V = 0. Design the required circuit using dual 4x1 MUXS and minimum additional logic.Available resources along with dual 4x1 MUXS are NOT gates, 2-input(AND, OR, NAND, NOR) gates.

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Given a 5-bit ADC with the following reference values Vref= -2V and 12V, what is the voltage represented by the output sequence 01010?

1What will be the state of a MOD64 counter after 90 input pulses if the starting state=000000?A.100100B.011010C.010110D.011100 2.A MOD 32 counter is holding the count 101112. What will the count be after 31 clock pulses?A.10100B.10010C.10000D.10110

Q2 - Pseudo-Random Number Generator a) The following circuit is a pseudo-random number generator which uses linear feedback shift registers to produce a stream of outputs. The XOR tap at index '1' is responsible for generating this sequence of outputs. Fill in the table for the outputs of the 4 registers after each clock cycle. The initial output state is already provided in the first row. You can stop when the output starts to repeat and just say that it is repeating. QO Q1 Q2 Q3 ID ClockEdge # Q3 Q2 Q1 QO 1 1 2 3 7 10 11 12 13 14 00

A sequence detector is designed to detect precisely 3 digital inputs, with overlapping sequences detectable. For the sequence (1,0,1) and input data (1,1,0,1,0,0,1,1,0,1,0,1,1,0), what is the output of this detector?

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3. The timing diagram below is for the 8-bit register block shown. Complete the timing diagram by filling in the output (q) signal. load q(N-1.0)+ cik cir Input(N-1.0) cik Register cir load input 45 A3 4B FF 44 01 02 CA 66 7A 98 9

Design a combinational circuit with the four inputs A,B.C, and D, and three outputs X, Y, and Z. When the binary input is odd number, the binary output is one lesser than the input. When the binary input is even number the binary output is one greate than the input. Implement the function using multiplexers with minimal input and select line.

Develop the Q output waveforms for a 74HC190 up/down counter with the input waveforms shown in figure below. A binary 0 is on the data inputs. Start with a count of 0000. CLK CTEN LOAD