Design a Mealy FSM that can detect the pattern ‘0110’ in a sequence of binary bits. a) Draw the state transition diagram b) Using binary state encoding, complete a combined state transition and output table and write the Boolean equations for the next state and output logic units. c) Sketch the FSM’s schematic.

a- Draw & explain the block diagram of synchronous sequentialcircuits.b- Design & draw a (3 × 2) binary digit multiplier, explaining itsmechanism of operation.

Figure Q7 describes a Linear Feedback Shift Register (LFSR). Draw the equivalent schematic diagram of the system based on an off-the-shelf shift register, clearly showing the number of exclusive-OR gates needed to construct it. LIBRARY ieee; USE ieee.std logic_1164.all; entity lfsr is CLK, RESET: in STD LOGIC; Q: out STD LOGIC_VECTOR (5 downto 0) ); port ( end lfsr; architecture behavior of lfsr is begin process (CLK,RESET) begin if RESET='1' then Q <= "000001"; else Q <= ( Q(3) xor Q(2) xor Q(0) ) & Q(5 downto 1); end if; end process; end behavior;

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Given the these minterms (4, 5, 6, 7, 8, 9, 10, 13, 14, 15), write a VHDL STATEMAENT for the function as a SOP. Please use this Entity Declaration in formulating the statement entity midterm is Port(A, B, C, D in STD_LOGIC; F: out STD_LOGIC); end midterm;

1. Draw the state diagram for a clocked synchronous state machine with two inputs, INIT and X, and one Moore-type output Z. As long as INIT is asserted, Z remains 0. Once INIT is negated, Z should remain 0 until X has been 0 for two consecutive ticks and 1 for two successive ticks (or vice versa). Then Z should go to 1 and remain 1 until INIT is asserted again. Assume that once INIT is negated, it will not be asserted again until sometime after Z goes to a 1. (Hint: No more than ten states are required.)

Design and implement (draw the circuit) the output f(12) of a 7 segments decoder as a function of the binary inputs (W,X,Y,Z). You need the complete the following steps: 1. Find the f(12) outputs values (0 or 1) for each number from 0-11 2. Enter these values into a Karnaugh map. 3. Simplify the map. 4. Draw the circuit using Tina. 7 segments display decoder. 7 segments 4 Binary inputs a 7 Segments Decoder Y e

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