In a DRAM chip, the row buffer capacity is 4KB. How many DRAM clock cycles will it take to transfer 1KB data using a burst mode with a 64-byte cache block/line and a memory that can transfer 64-bit data over the bus? Assume the row is always pre-charged. Hint: Add the precharge cycles every time a row buffer is closed, recall row buffer acts as a small cache. Assume: -5 cycles to send row address (page open or RAS) -1 cycle to send a column address -3 cycle DRAM access latency -1 cycle to send data -5 cycles to send precharge (page close)

Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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Question 5
In a DRAM chip, the row buffer capacity is 4KB. How many DRAM clock cycles will it take to transfer 1KB data
using a burst mode with a 64-byte cache block/line and a memory that can transfer 64-bit data over the bus?
Assume the row is always pre-charged.
Hint: Add the precharge cycles every time a row buffer is closed, recall row buffer acts as a small cache.
Assume:
-5 cycles to send row address (page open or RAS)
-1 cycle to send a column address
-3 cycle DRAM access latency
-1 cycle to send data
-5 cycles to send precharge (page close)
Transcribed Image Text:Question 5 In a DRAM chip, the row buffer capacity is 4KB. How many DRAM clock cycles will it take to transfer 1KB data using a burst mode with a 64-byte cache block/line and a memory that can transfer 64-bit data over the bus? Assume the row is always pre-charged. Hint: Add the precharge cycles every time a row buffer is closed, recall row buffer acts as a small cache. Assume: -5 cycles to send row address (page open or RAS) -1 cycle to send a column address -3 cycle DRAM access latency -1 cycle to send data -5 cycles to send precharge (page close)
Question 6
Using the above DIMM, how many times memory controller will send the pre-charge command when reading 24KB
data? Assume before starting the read pre-charge command was issued.
Transcribed Image Text:Question 6 Using the above DIMM, how many times memory controller will send the pre-charge command when reading 24KB data? Assume before starting the read pre-charge command was issued.
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