QUESTION 1: If a CPU has 32 address lines for address bus and 64 bits' data buses. Answer the following questions: a) Show the design of fully associative L1 cache with 212 rows. b) Show the design of direct mapped cache with 216 row rows.

QUESTION 1: If a CPU has 32 address lines for address bus and 64 bits' data buses. Answer the following questions: a) Show the design of fully associative L1 cache with 212 rows. b) Show the design of direct mapped cache with 216 row rows.

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter11: Operating Systems

Section: Chapter Questions

Problem 30VE

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Fundamentals of Input and Output Performance

The I/O subsystem is a component of computer system design that uses buses to assist communication between the Central Processing Unit, Computer Memory/Storage, and Input and Output Devices (that is known as peripheral devices). The I/O subsystem includes disc controllers, tape drives, discs, system buses, and other devices. The I/O database application reads and writes drives using the operating system windows I/O.

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