Assume the cache miss penalty is 100 clock cycles and all instructions normally take 1.0 clock cycles (ignoring memory stalls). Assume the average miss rate is 2%, there is an average of 1.5 memory references for instruction, and the average number of cache misses per 1000 instructions is 30. What is the impact on performance when behavior of the cache is included? Calculate the impact using both misses per instruc- tion and miss rate.

Database System Concepts
7th Edition
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
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Assume the cache miss penalty is 100 clock cycles and all instructions normally take
1.0 clock cycles (ignoring memory stalls). Assume the average miss rate is 2%, there
is an average of 1.5 memory references for instruction, and the average number of
cache misses per 1000 instructions is 30. What is the impact on performance when
behavior of the cache is included? Calculate the impact using both misses per instruc-
tion and miss rate.
Transcribed Image Text:Assume the cache miss penalty is 100 clock cycles and all instructions normally take 1.0 clock cycles (ignoring memory stalls). Assume the average miss rate is 2%, there is an average of 1.5 memory references for instruction, and the average number of cache misses per 1000 instructions is 30. What is the impact on performance when behavior of the cache is included? Calculate the impact using both misses per instruc- tion and miss rate.
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