QUESTION 9 1. If a given memory address for a byte addressable machine is found in a cache that uses a 128 byte cache line size, the least significant 8 bits in the memory address will be used to select the byte(s) in the cache line to work with. True False QUESTION 10 1. SRAM memory is used predominately in: C SRAM memory is used predominately in: C motherboard main memory C BIOS PROM memory C SD card memory devices C CPU on-chip cache memory

QUESTION 9 1. If a given memory address for a byte addressable machine is found in a cache that uses a 128 byte cache line size, the least significant 8 bits in the memory address will be used to select the byte(s) in the cache line to work with. True False QUESTION 10 1. SRAM memory is used predominately in: C SRAM memory is used predominately in: C motherboard main memory C BIOS PROM memory C SD card memory devices C CPU on-chip cache memory

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 2PE: If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the...

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Assume we have a computer with 512 blocks of cache memory with a total capacity of 128K bits. Answer the following questions knowing that the computer operates in a word addressable mode and that the format of the memory address as perceived by the Fully associative cache scheme is as shown below: Cache Format with Full Associativity 19 5 1- How many words are in each cache block? 2- How big are the letters in each word? 3- How large is the primary memory? 4- What is the total number of blocks in main memory? 5- Draw the memory address format as observed by the Direct Mapped Cache technique, including the fields and their sizes.
Assume that we are having a computer with the following characteristics: 1MB of main memory; word size of 1 byte; block size of 16 bytes; and cache size of 64 KB. For the main memory addresses of FF010, the corresponding set number for a four-way set associative cache will be?
Assume that we have a computer with a cache memory of 512blocks with a total size of 128K bits. Knowing that the computer uses a word addressable mode and the format of the memory address as seen by the Fully associative cache scheme is as shown below, answer the below questions: Fully Associative Cache Format 1- How many words do we have in each cache block? 2- What is the size of each word? 3- What is the size of the main memory? 4- How many blocks are there in the main memory? 5- Draw the format of the memory address as seen by the Direct Mapped Cache scheme, showing the fields as well as their sizes.
Assume that we have a computer with a cache memory of 512 blocks with a total size of 128K bits. Knowing that the computer uses a word addressable mode and the format of the memory address as seen by the Fully associative cache scheme is as shown below, answer the below questions: Fully Associative Cache Format 19 5 1- How many words do we have in each cache block? 2- What is the size of each word? 3- What is the size of the main memory? 4- How many blocks are there in the main memory? 5- Draw the format of the memory address as seen by the Direct Mapped Cache scheme, showing the fields as well as their sizes.
Suppose a byte-addressable computer using set associative cache has 8M byes of main memory and a cache of 128 blocks, where each cache block contains 64 bytes. a) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and offset fields? b) If this cache is 16-way set associative, what is the format of a memory address as seen by the cache
I am confused A memory system has a 32 KB byte-addressable main memory and a 1 KBcache where each block contains 16 bytes. Determine the format of the address in each of thecache organizations. In each case list the address fields and the width of each field.a) Direct-mapped cacheb) Fully-associative cachec) 4-way set-associative cache
Suppose a byte-addressable computer using set-associative cache has 216 bytes of main memory and a cache of 32 blocks, and each cache block contains 8 bytes.Q.) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache?
Suppose a byte-addressable computer using set associative cache has 224 bytes of main memory and a cache size of 64K bytes, and each cache block contains 32 bytes. a) If this cache is 2-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and offset fields? b) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache?
Suppose a byte-addressable computer using set associative cache has 4Mbyes of main memory and a cache of 64 blocks, where each cache block contains 8 bytes. a) If this cache is 2-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and offset fields? b) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache? Show all work and explain how you got the answers please. Thanks
Let's pretend for a moment that we had a byte-addressable computer with 2-way set associative mapping, 16-bit main memory addresses, and 32 cache memory blocks at our disposal. Using the information that there are 8 bytes in each block, calculate the size of the offset field and show your results.
For the following two questions assume that a computer uses a byte-addressable virtual memory system with a two-entry TLB, a 2-way set associative cache, and a page table for a process P. Assume cache blocks of size 8 bytes. Assume pages of size 16 bytes and a main memory of 4 frames. Assume the following TLB and page table for Process P: TLB 0 3 4 1 Page Table Frame Valid 0 3 1 1 0 1 2 - 0 3 2 1 4 1 1 5 - 0 6 - 0 7 - 0 Question 11 Show the address format for virtual address 0x43. Page Offset Question 11 options: Question 12 What physical address will be used for virtual address 0x12. Frame Offset
. Consider a system that has multiple processors where eachprocessor has its own cache, but main memory is shared among allprocessors.1. a) Which cache write policy would you use?2. b) The cache coherency problem. With regard to the systemjust described, what problems are caused if a processor has acopy of memory block A in its cache and a second processor,also having a copy of A in its cache, then updates mainmemory block A? Can you think of a way (perhaps morethan one) of preventing this situation, or lessening itseffects?