R1 = X + 1 Y = R1 + R2 R1 = R2 + X Complete the following: Lay the instructions out as they would be fed through a 6-stage CPU pipeline not accounting for any hazards. S1: Fetch instruction, S2: Decode opcode, S3: Calc effective address of operands, S4: Fetch operands, S5: Execute instruction, S6: Store result Identify any hazards present "Fix" the pipeline process to remove the hazards

Database System Concepts
7th Edition
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Chapter1: Introduction
Section: Chapter Questions
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This was previously asked and answered, but I need it in a format similar to what is depicted in the image attached, but with 6 stage instead of 4 stage. 

R1 = X + 1
Y = R1 + R2
R1 = R2 + X

Complete the following:

  1. Lay the instructions out as they would be fed through a 6-stage CPU pipeline not accounting for any hazards.

S1: Fetch instruction, S2: Decode opcode, S3: Calc effective address of operands, S4: Fetch operands, S5: Execute instruction, S6: Store result

  1. Identify any hazards present
  2. "Fix" the pipeline process to remove the hazards
Practice out in the pipeline...
Fixed with NoOps inserted
Time
Period
10 11
1
2
3
4
5
6
8
9
12
X =
S1
S4
R1 +
Fetch
S2
S3
Store
10
R1
X
S1
S4
R1 =
No
No
No
Fetch
S2
S3
Store
X + Y
Op
Op
Op
X & Y
R1
S1
R2 =
S4
No
No
No
No
No
No
Fetch
R1 +
s2 S3
Store
Op
Op
Op
Op
Op
Op
R1 &
Y
R2
Y
S1. Fetch. S2. Decode. S3. Execute. S4. Store.
Transcribed Image Text:Practice out in the pipeline... Fixed with NoOps inserted Time Period 10 11 1 2 3 4 5 6 8 9 12 X = S1 S4 R1 + Fetch S2 S3 Store 10 R1 X S1 S4 R1 = No No No Fetch S2 S3 Store X + Y Op Op Op X & Y R1 S1 R2 = S4 No No No No No No Fetch R1 + s2 S3 Store Op Op Op Op Op Op R1 & Y R2 Y S1. Fetch. S2. Decode. S3. Execute. S4. Store.
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