We want to compare the latency and the cycle time of a pipelined and non-pipelined processor design. Assume that individual stages of the datapath have the following latencies: IF ID EX MEM WB 250ps 350ps 150ps 300ps 200ps a. What is the clock cycle time in a pipelined and non-pipelined processor? b. What is ld instruction latency in a pipelined and non-pipelined processor? c. Assume 10 consecutive instructions are executed in the pipelined and the non-pipelined processors. What is the total execution time on the two processors? Note that there is no data or control dependences among the 10 instructions.

We want to compare the latency and the cycle time of a pipelined and non-pipelined processor design. Assume that individual stages of the datapath have the following latencies: IF ID EX MEM WB 250ps 350ps 150ps 300ps 200ps a. What is the clock cycle time in a pipelined and non-pipelined processor? b. What is ld instruction latency in a pipelined and non-pipelined processor? c. Assume 10 consecutive instructions are executed in the pipelined and the non-pipelined processors. What is the total execution time on the two processors? Note that there is no data or control dependences among the 10 instructions.

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 10RQ: How does pipelining improve CPU efficiency? What’s the potential effect on pipelining’s efficiency...

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