INTRO.TO COMPUTING SYSTEMS >INTL.ED.<
3rd Edition
ISBN: 9781260565911
Author: PATT
Publisher: MCG
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Chapter 4, Problem 19E
Shown below is a byte-addressible memory consisting of eight locations, and its associated MAR and MDR. Both MAR and MDR consist of flip-flops that are latched at the start of each clock cycle based on the values on their corresponding input lines. A memory read is initiated every cycle, and the data is available by the end of that cycle.
Just before the start of cycle 1, MAR contains 000, MDR contains 00010101, and the contents of each memory location is as shown.
a. What do MAR and MDR contain just before the end of cycle 1?
MAR: 
MDR: 
b. What does MDR contain just before the end of cycle 4?
MDR: 
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In a dynamic random access memory (DRAM) computer chip, each memory cell chiefly consists of a capacitor for charge storage. Each of these cells represents a single binary-bit value of 1 when its 35-fFfcapacitor (1fF=10^−15F) is charged at 1.5 V, or 0 when uncharged at 0 V.
A)When it is fully charged, how many excess electrons are on a cell capacitor's negative plate?
B)
After charge has been placed on a cell capacitor's plate, it slowly "leaks" off (through a variety of mechanisms) at a constant rate of 0.30 fC/s. How long does it take for the potential difference across this capacitor to decrease by 1.0% from its fully charged value? (Because of this leakage effect, the charge on a DRAM capacitor is "refreshed" many times per second.)
Express your answer to two significant figures and include the appropriate units.
D-Latch is a simple clocked memory element in which the output is equal to the stored state inside the element.
In D-Latch the state is changed whenever the appropriate inputs change and the clock is asserted. A D-Latch has two inputs and two outputs.
The inputs are the data value to be stored and a clock signal that indicates when the latch should read the value on the data input and store it. The outputs are simply the value of the internal state and its complement.
When the clock input is asserted, the latch is said to be open, and the value of the output becomes the value of the data input. When the clock input is de-asserted, the latch is said to be closed, and the value of the output is whatever value was stored the last time the latch was open.
What is the difference between DFF and D-Latch?
Can one chip be used for constructing the other? Explain.
A digital computer has a memory unit with 24 bits per word. The instruction set consists of 150 different operations. All instructions have an operation code part (opcode) and an address part (allowing for only one address). Each instruction is stored in one word of memory.Q.) What is the maximum allowable size for memory?
Chapter 4 Solutions
INTRO.TO COMPUTING SYSTEMS >INTL.ED.<
Ch. 4 - Prob. 1ECh. 4 - Prob. 2ECh. 4 - What is misleading about the name program counter?...Ch. 4 - Prob. 4ECh. 4 - Prob. 5ECh. 4 - What are the two components of an instruction?...Ch. 4 - Prob. 7ECh. 4 - The FETCH phase of the instruction cycle does two...Ch. 4 - Prob. 10ECh. 4 - State the phases of the instruction cycle, and...
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