Chapter 4.2, Problem 4.12PP

Program Plan Intro

Combinational circuits and HCL expressions:

• The computational blocks are been constructed by assembling several logic gates into network.
• The restrictions are been shown below:
  • Each of input for logic gate should be associated to any one shown below:
    • One of system inputs, that is identified as primary inputs.
    • Output connection for some element in memory.
    • Output of some logic gate.
  • Outputs obtained from more than two logic gates could not be linked together.
    • The wire would be driven to different voltages.
    • It can cause malfunction in circuit.
  • The network should not contain cycles.
    • The loops in circuit can cause ambiguity in function computed by network.
• The “HCL” denotes a hardware control language that is used for describing control logic of different processor designs.