Computer Systems: A Programmer's Perspective (3rd Edition)
3rd Edition
ISBN: 9780134092669
Author: Bryant, Randal E. Bryant, David R. O'Hallaron, David R., Randal E.; O'Hallaron, Bryant/O'hallaron
Publisher: PEARSON
expand_more
expand_more
format_list_bulleted
Question
Chapter 4.3, Problem 4.25PP
Program Plan Intro
Processing stages:
- The processing of an instruction has number of operations.
- The operations are organized into particular sequence of stages.
- It attempts to follow a uniform sequence for all instructions.
- The description of stages are shown below:
- Fetch:
- It uses program counter “PC” as memory address to read instruction bytes from memory.
- The 4-bit portions “icode” and “ifun” of specifier byte is extracted from instruction.
- It fetches “valC” that denotes an 8-byte constant.
- It computes “valP” that denotes value of “PC” plus length of fetched instruction.
- Decode:
- The register file is been read with two operands.
- It gives values “valA” and “valB” for operands.
- It reads registers with instruction fields “rA” and “rB”.
- Execute:
- In this stage the ALU either performs required operation or increments and decrements stack pointer.
- The resulting value is termed as “valE”.
- The condition codes are evaluated and destination register is updated based on condition.
- It determines whether branch to be utilized in a jump instruction.
- Memory:
- The memory has data written into it or read operation is done from memory.
- The value that is read is determined as “valM”.
- Write back:
- The results are been written to register file.
- It can write up to two results.
- PC update:
- The program counter “PC” denotes memory address to read bytes of instruction from memory.
- It is used to set next instruction’s address.
- Fetch:
Combinational circuits and HCL expressions:
- The computational blocks are been constructed by accumulating several logic gates into network.
- The restrictions are been shown below:
- Each of input for logic gate should be connected to any one shown below:
- One of system inputs, that is identified as primary inputs.
- Output connection for some element in memory.
- Output of some logic gate.
- Outputs obtained from more than two logic gates could not be linked together.
- The wire would be driven to different voltages.
- It can cause malfunction in circuit.
- The network should not contain cycles.
- The loops in circuit can cause ambiguity in function
computed by network.
- The loops in circuit can cause ambiguity in function
- Each of input for logic gate should be connected to any one shown below:
- The “HCL” denotes a hardware control language that is used for describing control logic of different processor designs.
Expert Solution & Answer
Want to see the full answer?
Check out a sample textbook solutionStudents have asked these similar questions
1. We wish to compare the performance of two different machines: M1 and M2. The following measurements have been made on these machines:
Program
Time on M1
Time on M2
1
10 seconds
5 seconds
2
3 seconds
4 seconds
Which machine is faster for each program, and by how much?
2. For M1 and M2 of problem 1, the following additional measurements are made:. Find the instruction execution rate (instructions per second) for each machine when running program 1.
Program
Instructions executed on M1
Instructions executed on M2
1
200 x 106
160 x 106
3. For M1 and M2 of problem 1, if the clock rates are 200 MHz and 300 MHz, respectively, find the CPI for program 1 on both machines using the data provided in problems 1 and 2.
4. You are going to enhance a machine, and there are two possible improvements: either make multiply instructions run four times faster than before or make memory access instructions run two times faster than before. You…
4.1.1
Complete solution and answer only no need explanation
Given three data points (1,6), (3,28), and (10, 231), What is the value of y at x = 2 if the function y = 2x2 + 3x + 1 passes through the three data points.
A program has the following breakdown:
25% ld (50% of them directly followed by a dependent instruction),25% sd, 30% r_type, 20% beq (80% of them are taken. Branches are calculated in the third cycle. What is the average CPI of the program when run on the pipelined RISC V implementation in the textbook?
Chapter 4 Solutions
Computer Systems: A Programmer's Perspective (3rd Edition)
Ch. 4.1 - Prob. 4.1PPCh. 4.1 - Prob. 4.2PPCh. 4.1 - Prob. 4.3PPCh. 4.1 - Prob. 4.4PPCh. 4.1 - Prob. 4.5PPCh. 4.1 - Prob. 4.6PPCh. 4.1 - Prob. 4.7PPCh. 4.1 - Prob. 4.8PPCh. 4.2 - Practice Problem 4.9 (solution page 484) Write an...Ch. 4.2 - Prob. 4.10PP
Ch. 4.2 - Prob. 4.11PPCh. 4.2 - Prob. 4.12PPCh. 4.3 - Prob. 4.13PPCh. 4.3 - Prob. 4.14PPCh. 4.3 - Prob. 4.15PPCh. 4.3 - Prob. 4.16PPCh. 4.3 - Prob. 4.17PPCh. 4.3 - Prob. 4.18PPCh. 4.3 - Prob. 4.19PPCh. 4.3 - Prob. 4.20PPCh. 4.3 - Prob. 4.21PPCh. 4.3 - Prob. 4.22PPCh. 4.3 - Prob. 4.23PPCh. 4.3 - Prob. 4.24PPCh. 4.3 - Prob. 4.25PPCh. 4.3 - Prob. 4.26PPCh. 4.3 - Prob. 4.27PPCh. 4.4 - Prob. 4.28PPCh. 4.4 - Prob. 4.29PPCh. 4.5 - Prob. 4.30PPCh. 4.5 - Prob. 4.31PPCh. 4.5 - Prob. 4.32PPCh. 4.5 - Prob. 4.33PPCh. 4.5 - Prob. 4.34PPCh. 4.5 - Prob. 4.35PPCh. 4.5 - Prob. 4.36PPCh. 4.5 - Prob. 4.37PPCh. 4.5 - Prob. 4.38PPCh. 4.5 - Prob. 4.39PPCh. 4.5 - Prob. 4.40PPCh. 4.5 - Prob. 4.41PPCh. 4.5 - Prob. 4.42PPCh. 4.5 - Prob. 4.43PPCh. 4.5 - Prob. 4.44PPCh. 4 - Prob. 4.45HWCh. 4 - Prob. 4.46HWCh. 4 - Prob. 4.47HWCh. 4 - Prob. 4.48HWCh. 4 - Modify the code you wrote for Problem 4.47 to...Ch. 4 - In Section 3.6.8, we saw that a common way to...Ch. 4 - Prob. 4.51HWCh. 4 - The file seq-full.hcl contains the HCL description...Ch. 4 - Prob. 4.53HWCh. 4 - The file pie=full. hcl contains a copy of the PIPE...Ch. 4 - Prob. 4.55HWCh. 4 - Prob. 4.56HWCh. 4 - Prob. 4.57HWCh. 4 - Our pipelined design is a bit unrealistic in that...Ch. 4 - Prob. 4.59HW
Knowledge Booster
Similar questions
- 1.BL=00, after instruction DEC BL is executed, CF =? 2.CH=80H; after ROL CH, 1; CH=?arrow_forwardli $t2, 2 L1: add $t1, $t1, $t2 sub $t1, $t1, $t3 bne $t1, $t4, L1 sub $t4, $s0, $t3 Given the modified single-cycle processor shown below, what are the values (in binary) of instruction[31-26], instruction[25-21], instruction[20-16], instruction[15-11], instruction[5-0], Read data 1, Read data 2, ALU zero, PCSrc, and all the main control decoded output signals when the time is at 1950 ns. The below single-cycle processor diagram can be used for your reference. Note: A new decoded signal output “Tzero” is added for executing “bne” instruction. The signal definition is described below: Instruction Opcode New Main Control Output Signal beq 00100b (4d) Tzero = 0 bne 00101b (5d) Tzero = 1 At the moment of 1950 ns, the below values (0, 1 or X) are:instruction[31-26] = instruction[25-21] = instruction[20-16] =instruction[15-0] = Read data 1 output = Read data 2 output = RegDst = ALUSrc = MemtoReg = RegWrite =…arrow_forwardProblem 10arrow_forward
- Problem 4: Give a block diagram for a 8M x 32 memory using 512K x 8 memory ch book] [Hints: Figure 5.10 in thearrow_forward4.18 [5] <COD §4.5> Assume that X1 is initialized to 11 and X2 is initialized to 22. Suppose you executed the code below on a version of the pipeline from COD Section 4.5 (An overview of pipelining) that does not handle data hazards (i.e., the programmer is responsible for addressing data hazards by inserting NOP instructions where necessary). What would the final values of registers X3 and X4 be? ADDI X1, X2, #5 ADD X3, X1, X2 ADDI X4, X1, #15arrow_forward1.3 Assemble the following assembly code into machine code. Assume that the machine language op-codes for load, store, mult, add, div, and sub are 18, 19, 13, 14, 15, and 16, respectively. Also assume that the variable x is stored at location M[50]. load R1, x mult R2, R1, #9 store x, R2 sub R0, R1, #8 div R2, R0, #2 I NEED THE MACHINE CODE IN DECIMAL PLEASE,arrow_forward
- Section 1.0 cites as a pitfall the utilization of a subset of the performace equation as a performance metric. To illustrate this, consider the following two processors. P1 has a clock rate of 4GHz, average CPI of 0.9, and requires the execution of 5.0E9 instructions. P2 has a clock rate of 3GHz, an average CPI of 0.75, and requires the execution of 1.0E9 instructions. (1) A common fallacy is to use MIPS to compare the performace of two different processors, and consider that the processor with the largest MIPS has the largest performance. Check if this is true for P1 and P2. (2) Another common performace figure is MFLOPS, defined as MFLOPS = No. FP operations / (execution time x 1E6) but this figure has the same problems as MIPS. Assume that 40% of the instructions executed on both P1 and P2 are floating-point instructions. Find the MFLOPS figures for the processors.arrow_forwardComputer Science Consider the following comparison instruction:TST R0, R1, ASR #1 ; R0 = 0x12345678 and R1 = 0xDB97530F(i) Appraise the value of the condition flags (N, Z, C, V) after the execution of the instruction. Use the values of R0 and R1 provided in the instruction comment.(ii) The conditional branches are BHS, BLO, BLT and BPL. From the condition flag bits appraised in Question 2(b)(i), determine which of the above conditional branches will be executed.arrow_forward- Consider that each instruction require 6 steps (phases) to execute and each (step) phase takes 5 seconds to complete. Also, within each instruction it requires 3 seconds time gap between end of completion one step (phase) and beginning of next step (phase). b. Design and reflec on a suitable pipeline technique using which time taken for executing all 3 programs can be further improved. Calculate the improved time using this method by considering that instruction require same number of steps to complete and time taken for each step is same and time gap between each steps is also same?arrow_forward
- 15.a) Consider an instruction pipeline with four stages with the stage delays 5 nsec, 6 nsec, 11 nsec, and 8 nsec respectively. The delay of an inter-stage register stage of the pipeline is 1 nsec. What is the approximate speedup of the pipeline in the steady-state underideal conditions as compared to the corresponding non-pipelined implementation? b) Discuss structural hazards and control hazards with examples pls answer both subparrts,,its urgent thanksarrow_forward1. In this exercise we examine in detail how an instruction is executed in a single cycle datapath. Problems in this exercise refer to a clock cycle in which the processor fetches the following instruction word: 10001100101001100000000000111000 Assume that the data memory is all zeros and that the processor’s registers have the following values at the beginning of the cycle in which the above instruction word is fetched: R0 R1 R2 R3 R4 R5 R6 R8 R12 R3 1 0 1 -2 4 -6 4 -10 -12 -14 31 a. What are the outputs of the sign-extend and the jump “Shift-Left-2” (near the top of the following Figure) for this instruction word? b. What are the values of ALU control unit’s inputs (ALUOp and Instruction operation) for this instruction? c. For the ALU and the two add units, what are their data input values? ALU Add (PC+4) Add (Branch) Input#1 Input#2 Input#1 Input#2 Input#1 Input#2arrow_forwardQ.) Do given c and d problem belowarrow_forward
arrow_back_ios
SEE MORE QUESTIONS
arrow_forward_ios
Recommended textbooks for you
- Database System ConceptsComputer ScienceISBN:9780078022159Author:Abraham Silberschatz Professor, Henry F. Korth, S. SudarshanPublisher:McGraw-Hill EducationStarting Out with Python (4th Edition)Computer ScienceISBN:9780134444321Author:Tony GaddisPublisher:PEARSONDigital Fundamentals (11th Edition)Computer ScienceISBN:9780132737968Author:Thomas L. FloydPublisher:PEARSON
- C How to Program (8th Edition)Computer ScienceISBN:9780133976892Author:Paul J. Deitel, Harvey DeitelPublisher:PEARSONDatabase Systems: Design, Implementation, & Manag...Computer ScienceISBN:9781337627900Author:Carlos Coronel, Steven MorrisPublisher:Cengage LearningProgrammable Logic ControllersComputer ScienceISBN:9780073373843Author:Frank D. PetruzellaPublisher:McGraw-Hill Education
Database System Concepts
Computer Science
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:McGraw-Hill Education
Starting Out with Python (4th Edition)
Computer Science
ISBN:9780134444321
Author:Tony Gaddis
Publisher:PEARSON
Digital Fundamentals (11th Edition)
Computer Science
ISBN:9780132737968
Author:Thomas L. Floyd
Publisher:PEARSON
C How to Program (8th Edition)
Computer Science
ISBN:9780133976892
Author:Paul J. Deitel, Harvey Deitel
Publisher:PEARSON
Database Systems: Design, Implementation, & Manag...
Computer Science
ISBN:9781337627900
Author:Carlos Coronel, Steven Morris
Publisher:Cengage Learning
Programmable Logic Controllers
Computer Science
ISBN:9780073373843
Author:Frank D. Petruzella
Publisher:McGraw-Hill Education