A)
Explanation of Solution
Cache entry and cache byte:
The program running on a machine references the 1-byte word at address “Ox0DD5”. Hexadecimal is a number system of base 16As and as hex system has 16 digits, the extra needed 6 digits are represented by the first 6 letters of English alphabet which means “ 0,1,2,3,4,5,6,7,8” represents “9,A,?B,?C,?D,?E,?F” respectively in decimal system.
First, one needs to convert the hexadecimal address into binary form:
One needs to consider the following set associative (S, E, B, m) = (8, 4, 4, 13). The derived value will be as follows:
The Index (CI):
B)
Explanation of Solution
Memory reference:
The address format (1 bit per box) for address “Ox0DD5” is hence represented as:
CT | CT | CT | CT | CT | CT | CT | CT | CI | CI | CI | CO | CO |
0 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 |
Want to see the full answer?
Check out a sample textbook solutionChapter 6 Solutions
Computer Systems: A Programmer's Perspective (3rd Edition)
- 4.19.16: [5] <COD §4.6>. In this exercise, we examine how pipelining affects the clock cycle time of the processor. Problems in this exercise assume that individual stages of the datapath have the following latencies: Also, assume that instructions executed by the processor are broken down as follows: (a) What is the clock cycle time in a pipelined and non-pipelined processor? (b) What is the total latency of an lw instruction in a pipelined and non-pipelined processor? (c) If we can split one stage of the pipelined datapath into two new stages, each with half the latency of the original stage, which stage would you split and what is the new clock cycle time of the processor? (d) Assuming there are no stalls or hazards, what is the utilization of the data memory? (e) Assuming there are no stalls or hazards, what is the utilization of the write-register port of the "Registers" unit? No hand written and fast answer with explanationarrow_forward4.22 [5] <§4.5> Consider the fragment of LEGv8 assembly below: STUR X16, [X6, #12] LDUR X16, [X6, #8] SUB X7, X5, X4 CBZ X7, Label ADD X5, X1, X4 SUB X5, X15, X4 Suppose we modify the pipeline so that it has only one memory (that handles both instructions and data). In this case, there will be a structural hazard every time a program needs to fetch an instruction during the same cycle in which another instruction accesses data. 4.22.1 [5] <§4.5> Draw a pipeline diagram to show were the code above will stall. 4.22.2 [5] <§4.5> In general, is it possible to reduce the number of stalls/NOPs resulting from this structural hazard by reordering code? 4.22.3 [5] <§4.5> Must this structural hazard be handled in hardware? We have seen that data hazards can be eliminated by adding NOPs to the code. Can you do the same with this structural hazard? If so, explain how. If not, explain why not. 4.22.4 [5] <§4.5> Approximately how many stalls would you expect this…arrow_forwardSection 1.0 cites as a pitfall the utilization of a subset of the performace equation as a performance metric. To illustrate this, consider the following two processors. P1 has a clock rate of 4GHz, average CPI of 0.9, and requires the execution of 5.0E9 instructions. P2 has a clock rate of 3GHz, an average CPI of 0.75, and requires the execution of 1.0E9 instructions. (1) A common fallacy is to use MIPS to compare the performace of two different processors, and consider that the processor with the largest MIPS has the largest performance. Check if this is true for P1 and P2. (2) Another common performace figure is MFLOPS, defined as MFLOPS = No. FP operations / (execution time x 1E6) but this figure has the same problems as MIPS. Assume that 40% of the instructions executed on both P1 and P2 are floating-point instructions. Find the MFLOPS figures for the processors.arrow_forward
- 4.18 [5] <COD §4.5> Assume that X1 is initialized to 11 and X2 is initialized to 22. Suppose you executed the code below on a version of the pipeline from COD Section 4.5 (An overview of pipelining) that does not handle data hazards (i.e., the programmer is responsible for addressing data hazards by inserting NOP instructions where necessary). What would the final values of registers X3 and X4 be? ADDI X1, X2, #5 ADD X3, X1, X2 ADDI X4, X1, #15arrow_forward(15pt) Assume that instruction cache miss rate is 2%, data cache miss rate is 10%, CPI (clock cycle per instruction) is 2 without any memory stall, and miss penalty is 100 cycles. In addition, assume that the frequency of loads/stores is 30%. (a) Compute CPI with memory stall. (b) When CPI without any memory stall becomes 1, compute CPI with memory stall. (c) If the CPU clock rate is doubled with the same memory when CPI without memory stall is 2, compute CPI with memory stall.arrow_forward1.BL=00, after instruction DEC BL is executed, CF =? 2.CH=80H; after ROL CH, 1; CH=?arrow_forward
- help for the mips code. dont use AI, divi is not using in mips. Q1)Suppose $t1 stores the base address of word array A and $s2 is associated with h, convert to the following instruction into MIPS. if A[m+3]<20: A[m+1] = 5 else: A[m] = 1Q2) Assume only $s1, $s2, $a0, $v0 registers can be used. Procedure calling convention MUST be followed. def func(x): a = x/3 if a == 20: return a else: return 1arrow_forwardAnswer only 3 and 4 Suppose memory has 256KB, OS use low address 20KB, there is one program sequence: (20) • Prog1 request 80KB, prog2 request 16KB, • Prog3 request 140KB • Prog1 finish, Prog3 finish; • Prog4 request 80KB, Prog5 request 120kb • Use first match and best match to deal with this sequence • (from high address when allocated) • (1)Draw allocation state when prog1,2,3 are loaded into memory? • (2)Draw allocation state when prog1, 3 finish? • (3)use these two algorithms to draw the structure of free queue after prog1 , 3 finish(draw the allocation descriptor information,) • (4) Which algorithm is suitable for this sequence ? Describe the allocation process?arrow_forward(Practice) a. Using Figure 2.14 and assuming the variable name rate is assigned to the byte at memory address 159, determine the addresses corresponding to each variable declared in the following statements. Also, fill in the correct number of bytes with the initialization data included in the declaration statements. (Use letters for the characters, not the computer codes that would actually be stored.) floatrate; charch1=M,ch2=E,ch3=L,ch4=T; doubletaxes; intnum,count=0; b. Repeat Exercise 9a, but substitute the actual byte patterns that a computer using the ASCII code would use to store characters in the variables ch1, ch2, ch3, and ch4. (Hint: Use Appendix B.)arrow_forward
- Suppose that a 32M x 16 main memory is built using 512K × 8 RAM chips and memory is word-addressable. (Please show detailed work) f) If high-order interleaving is used, where would address 32(base 10) be located? (Your answer should be "Bank#, Offset#") g) Repeat (f) for low-order interleaving.arrow_forwardSUBJECT: COMPUTER ORGANASATION 1. a. How many address bits are required to access 256K words of memory? b. How many bytes of memory can be addressed by 24 address bits?arrow_forwardProblem 4: Give a block diagram for a 8M x 32 memory using 512K x 8 memory ch book] [Hints: Figure 5.10 in thearrow_forward
- C++ for Engineers and ScientistsComputer ScienceISBN:9781133187844Author:Bronson, Gary J.Publisher:Course Technology Ptr