Microelectronic Circuits (The Oxford Series in Electrical and Computer Engineering) 7th edition
7th Edition
ISBN: 9780199339136
Author: Adel S. Sedra, Kenneth C. Smith
Publisher: Oxford University Press
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Chapter 7, Problem 7.82P
To determine
The maximum value of the output resistance, drain current and the overdrive voltage.
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Gain of the amplifier falls of at high frequency due to internal capacitance of MOSFET. Determine the capacitances between different terminals of MOS transistor when it is operating in linear region at the drain to source voltage of 1 V. Device geometry and parasitic capacitances of MOSFET are: Gate oxide thickness 5 nm, channel length of 0.25 μm, width of the transistor 5 μm, gate overlap/lateral diffusion 10 % of channel length, junction capacitances at zero bias Csb0=Cdb0= 10 fF, built in potential of 0.4 V. Potential difference between source and bulk is 0.4 V
NPN BJTs can be used as emitter followers. In the given circuit, the emitter follower is connected to a non-ideal voltage source (Vs) with a source resistance (Rs). Beta is 100, Vce,sat is 0V, and Vbe is 0.7V.
1. What is Vo if Vs = 3V and Rs = 5k ohms?
2. What is Vo if Vs = 3V and Rs = 0 ohms?
Find the short-circuit time constants and fL for the common-source amplifier As Shown if ID = 1.5 mA and VGS−VTN = 0.5 V. Assume λ = 0.015/V. The other values remain unchanged.
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Microelectronic Circuits (The Oxford Series in Electrical and Computer Engineering) 7th edition
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- The parameters of the mosfets in the circuit formed with Qn (NMOS) and Qp (PMOS) elements are as follows: kn '(Wn / Ln) = kp'Wp / Lp = 1mA / V, Vtn = -Vtp = 1V, Δn = Δp = 0. When Vı = 0V, Vı = 2.5V, Vı = -2.5V, find the values of İDN, İDP and V0.arrow_forwardA source follower is required to connect a high-resistance source to a load whose resistance is nominally 2 k but can be as low as 1.5 k and as high as 5 k. What is the maximum output resistance that the source follower must have if the output voltage is to remain within ±10% of nominal value? If the MOSFET has kn = 2.5 mA/V2 , at what current ID must it be biased? At what overdrive voltage is the MOSFET operating?arrow_forwardA C-S amplifier is operating from a single 18-V supply. The MOSFET has Kn = 1 mA/V2. What is the Q-point current required for a voltage gain of 30?arrow_forward
- Refer to the Image Attached. Neglect the Early effect (that is, assume ro = ∞) and assume |VBE| = 0.7V. For VA = VB = 0V and neglecting all base currents, design the circuit so that each of Q1 and Q2 operates at a dc bias current of 0.4 mA, VC = VD = +10V, VE = 0V, and Q5 operates at a dc bias current of 1.8 mA. Specify the dc bias current at which each of Q3 and Q4 will be operating and give the required values of R1, R2, R3, R4, and R5. If β = 100, what must the value of each of the two resistances labeled Re be to obtain an input differential resistance of 54 kΩ? Find the differential voltage gain of the input stage, Q1−Q2. Find the voltage gain of the second stage, Q3−Q4. Find the voltage gain of the output stage, Q5. Find the overall voltage gain, vout/vid, where vout is the ac output voltage at node E, and vid is the differential input between the bases of Q1 and Q2.arrow_forwardThe dc bias circuit for a common emitter amplifier is shown in the figure. In the circuit, Vcc=15v,RB1=20k Ω,RB2=100k Ω,Rc=5.1k Ω,and RE1=1k Ω, Assume that when the transistor is on, the voltage drop from base to emitter VBE=0.7v. Also assume that β= ∞, which implies that the base current can be considered zero (IB=0) in your calculations. Solve for the base voltage VB. Solve for the emitter voltage VE. Solve for the emitter current IB. Solve for the collector current ICarrow_forwardWhat is the minimum bandwidth of the NMOS current mirror as shown if IS = 150 μA, K n = 25 μA/V2, λ = 0.02 V−1, CGS1 = 3 pF, CGD1 = 0.5 pF, and (W/L)1 = 5/1 = (W/L)2?arrow_forward
- A certain NMOS transistor has vGS(t) =2 V vDS(t) =5+2 sin(ωt) V iD(t) =3+0.01 sin(ωt) mA Which small-signal parameter (gm or rd) can be determined from this information? What is its value? For what Q point (VGSQ, IDQ and VDSQ) does this parameter apply?arrow_forwardGiven: Voltage Divider Bias Circuit Supply: 10Vdc to 24Vdc Load: 1000 ohms Voltage Gain: 80 to 400 Lower Cutt off Frequency: 100Hz Sinusoidal source (zero internal resistance): 50mVp-p Transistor: Si, beta=75 Base-Collector Capacitance= 8pF Base-Emitter Capacitance= 25pF Design a Single-stage Common Emitter Class A Amplifier and compute the following: a) dc load line b) hie c) midband gain d) Miller equivalent Capacitances e) upper cut off frequencyarrow_forwardAnother small-signal model, the “T-model” shown, is of historical interest and quite useful in certain situations. Show that this model is equivalent to the hybrid-pi model if the emitter resistance re = rπ/(βo + 1) = αo/gm = VT /IE . (Hint: Calculate the short-circuit input admittance (y11) for both models assuming βF = βo.)arrow_forward
- A MOSFET device is said to have a drain current of 1mA in the saturation region when VDS=0.5V. If VDS is changed to 1V, calculate how theID changes and find the output impedance.arrow_forwarda. What collector current is required for a bipolar transistor to achieve a transconductance of 5.5 mS ? Use VT=0.026V and express your answer in µA up to 2 decimal places. b. A transistor operating with nominal gm of 80 mS has a ββ that ranges from 50 to 150. Also, the bias circuit, being less than ideal, allows a 20% variation in ICIC. What is the smallest value found of the resistance looking into the base, in kΩkΩ? Use VT=0.026VT=0.026V and express your answer up to 3 decimal places. c. Given that a BJT is biased to have a small signal input resistance rπ = 25 kΩkΩ with β = 100, what is the BJT's transconductance gmgm? Use VT=0.026VT=0.026V and express your answer in mS and up to 2 decimal places.arrow_forwardIn the circuit in the figure, VGSQ = 6.8 V, IDQ = 2.4 mA, VGS(Th) = 3.3 V, k = 0.4x10-3 A/V2, RD = 5.6 kΩ, RF = 2.2 MΩ and rd = 25 kΩ. Accordingly, when a RL = 0.1 kΩ load is connected to the output of the circuit, what will be the voltage gain of the circuit? NOTE: MOSFET output resistance must be taken into account in rd calculationsarrow_forward
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