Microelectronic Circuits (The Oxford Series in Electrical and Computer Engineering) 7th edition
7th Edition
ISBN: 9780199339136
Author: Adel S. Sedra, Kenneth C. Smith
Publisher: Oxford University Press
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For the circuit shown in Fig. P7.53. draw a complete small-signal equivalent circuit utilizing an appropriate T model for the BJT (use alpha= 0.99). Neglect the transistor output resistance r0. Your circuit should show the values of all components, including the model parameters. What is the input resistance Rin? Calculate the overall voltage gain (vo/vsig).
For the follower circuit in Fig. P7.137, let transistor Q1 have β = 50 and transistor 2 have β = 100, and neglect the effect of ro. Use VBE = 0.7V
(a) Find the dc emitter currents of Q1 and Q2. Also, find the dc voltages VB1 and VB2.(b) If a load resistance RL = 1 kΩ is connected to the output terminal, find the voltage gain from the base to the emitter of Q2, , vo/vb2, and find the input resistance Rib2 looking into the base of Q2. (Hint: Consider Q2 as an emitter follower fed by a voltage Vb2 at its base).(c) Replacing Q2 with its input resistance Rib2 found in (b), analyze the circuit of emitter follower Q1 to determine its input resistance Rin, and the gain from its base to its emitter, ve1/vb1(d) If the circuit is fed with a source having a 100 kΩ resistance, find the transmission to the base of Q1, Vb1/Vsig(e) Find the overall voltage gain Vo/Vsig
It is required to design the bias circuit of Fig. 7.52 for a BJT whose nominal β=100.
(a) Find the largest ratio (RB/RE) that will guarantee IE remains within ±5% of its nominal value for β as low as 50 and as high as 150 .
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- Please answer immediately and correctly. The circuit shown is a common source amplifier with a current mirror bias. It is given that the NMOS (M1) parameters are μoCox = 3mA/V2, VTH,n = 0.5V and λ = 0.02 and the PMOS (M2 and M3) parameters are μoCox = 1mA/V2 and VTH,p = −0.6V . The PMOS transistor M3 does not have channel length modulation while PMOS transistor M2 has λ = 0.02. It is also given that the dimensions of M2 and M3 have equal widths of 5µm and lengths of L2 = 3µm and L3 = 1.5µm, respectively. M1 has length of L1 = 1µm and width of W1 = 2µm. Find kp and kn.arrow_forward5. Choose the correct answer: a) The reason of high input resistance of the MOSFET is: 1. The insulator layer. 2. The reverse biasing. 3. The forward biasing. b) Which transistor has no Ipss parameter?. 1. JFET. 2. E-MOSFET. 3. D-MOSFET. ¢) For an n-channel D-MOSFET transistor, at what condition can gm be greater than gmo?. 1. Vs is positive. 2. Vgs is negative. 3. Vas =0. d) A certain amplifier has an Rp=1KQ. When a load resistance of 1KQ is capacitively coupled to the drain, the gain will reduce to the: 1. Half. 2. Quarter. 3. Not change.arrow_forwardAn npn transistor with IS = 1 × 10−16 μA, αF =0.975, and αR = 0.5 is operating with VB E = 0.70 Vand VBC = 0.50 V. By definition, this transistor isoperating in the saturation region. However, in thediscussion it was noted that this transistor actually behaves as if it is still in the forwardactive region even though VBC > 0. Why? Use thetransport model equations to justify your answerarrow_forward
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- Determine the small-signal model of Q1 for the circuit above. (IS = 8 × 10−16 A, β = 100, and VA =∞. ) (Find the values of gm , rπ)arrow_forwardAn NMOS transistor has μn = 400 cm2/V-sec, L = 0.5 mand is biased at 0.25 V above threshold. What value of LS is required to achieve an input resistance of 75 Ω as shown.arrow_forward5.1 A 0.18-um fabrication process is specified to have t = 4 nm, µ̟ = 450 cm'/N s, and V, = 0.5 V. Find the value of the process transconductance parameter k. For a MOSFET with minimum length %3D fabricated in this process, find the required value of W so that the device exhibits a channel resistance Ing of 1 k£2 at vos =1 V. %3Darrow_forward
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