EECS140_Lab 8

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School

University of Kansas *

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140

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Mechanical Engineering

Date

Jan 9, 2024

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docx

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4

Uploaded by ColonelElectronDolphin32

Lab 8:EECS 140 ALU1 Arithmetic Logic Unit Objectives The objective of this laboratory is to apply knowledge of combinational logic designs to real world application by implementing an arithmetic logic unit into a field programmable gate array chip which can do addition, AND, OR and XOR operations. Discussion Figure 1: Flow chart for ALU
Figure 2: Internal Signals for ALU Click here to view the ALU block diagram (higher quality) The concept is to design and implement an arithmetic logic unit, which will have the ability to take two four bit binary numbers and depending on a two bit selector either add, logic AND, logic OR, or logic XOR the two inputs for a five bit binary output. You will use two seven-segment displays to display the binary output in hexadecimal format. Your inputs will range from the hexadecimal numbers 0 to F. Likewise, your outputs will range from 0 to 1E. In this lab you would be inserting the ripple carry adder design from your previous lab and the 7- segment display unit to display hexadecimal numbers. The code for the other components of the ALU is given to you below. Make sure you design your ALU component (toplevel) with the inputs and outputs of your existing components (adder, display, etc) in mind. Files Download and Add these source files to your new project in xilinx ISE project navigator. (Right click- >Save link as). Also change the file extension to .vhd Task s ANDer.vhd 4-bit And-gate ORer.vhd 4-bit Or-gate XORer.vhd 4-bit Xor-gate ADDer.vhd 4-bit Adder-gate function_select.vhd Multiplexer display_driver.vhd 7 segment driver LEDdisplay.vhd 7 segment Multiplexer Bit_full_adder.vhd 1 bit full adder (goes in the design of ADDER.vhd, already included) Toplevel_lab8.vhd Toplevel VHDL code Pre Lab 1. Declare components in toplevel.vhd 2. Instantiate (port mapping) components as per design 3. Write constraints file based on toplevel Entity. 4. Set control switches(00,01,10,11) to see results of ADD,OR,XOR,AND operations Please answer the following questions and submit to your TA at the start of the lab:
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