Performance Equations Consider a branch instruction which is executed 8 times in a program. Theactual outcomes of the branch are N, T, N, T, N,N,N, T where T =Taken and N = Not taken. Dynamic branch prediction is used to predict thebranch outcomes. Show the predictions made for each instance of thebranch and calculate the branch prediction accuracy in case of thefollowing two predictors:a) A 1-bit branch predictor which starts in the LNT (Likely Not Taken)stateAssume states to beSLT - Strongly Likely to be Taken (11)LT - Likely to be Taken (10)NLT - Not Likely to be taken (01) SNT - StronglyNot Likely to be taken(00)(b) A 2-bit branch predictor which starts in the SNT stateN.B. drawing the state diagram can help solve the problem easily.

Finally, we examined two distinct branch predictors' performances for a set of branch instructions.…

Answered: Consider a branch instruction which is…

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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This exercise examines the accuracy of various branch predictors for the following repeating pattern (e.g., in a loop) of branch outcomes: T, NT, T, T, NT What is the accuracy of the two-bit predictor if this pattern is repeated forever?
Suppose that we have an atomic test-and-set-lock instruction that atomically copies val to old_val, and sets val to 1. void test_and_set(int* old_val, int* val); Write the implementations for the following functions of a Spinlock. void acquire(int* lock) { // your code } void release(int* lock) { // your code } PROVIDE CODE IN C
The importance of having a good branch predictor depends on how often conditional branches are executed. Together with branch predictor accuracy, this will determine how much time is spent stalling due to mispredicted branches. In this exercise, assume that the breakdown of dynamic instructions into various instruction categories is as follows: R-Type BEQ JMP LW SW 40% 25% 5% 25% 5% Also, assume the following branch predictor accuracies: Always - Taken Always - not - taken 2-bit 40% 60% 75% 1.1 Stall cycles due to mispredicted branches increase the CPI. What is the extra CPI due to mispredicted branches with the always-taken predictor? Assume that branch outcomes are determined in the EX stage, that there are no data hazards, and that no delay slots are used. 1.2 Repeat 1.1 for the “always-not-taken” predictor. 1.3 Repeat 1.1 for the 2-bit predictor. 1.4 With the 2-bit predictor, what speedup would be achieved if we could convert half of the branch instructions in a way…
In this exercise we compare the performance of 1-issue and 2-issue processors, taking into account program transformations that can be made to optimize for 2-issue execution. Problems in this exercise refer to the following loop(written in C):for(i=0;i!=j;i+=2)b[i]=a[i]–a[i+1];When writing MIPS code, assume that variables are kept in registers as follows, and that all registers except those indicated as Free are used to keep various variables, so they cannot be used for anything else. i j a b c Free R5 R6 R1 R2 R3 R10,R11,R12 Translate this C code into MIPS instructions. Your translation should be direct, without rearranging instructions to achieve better performance.
This exercise examines the accuracy of various branch predictors for the following repeating pattern (e.g., in a loop) of branch outcomes: T, NT, T, T, NT What is the accuracy of the two-bit predictor for the first 4 branches in this pattern, assuming that the predictor starts off in the bottom left state from Figure 4.63 (predict not taken)? FIGURE IS ATTACHED, THANKS
What happens if VA page 30 is written even if an instruction was not accepted? An instance of a software-managed TLB would outperform a hardware-managed TLB in the following cases:
In this exercise we examine in detail how an instruction is executed in a single-cycle datapath. Problems in this exercise refer to a clock cycle in which theprocessor fetches the following instruction word: 10101100100001010000000000011100 Assume that the data memory is all zeros and that the processor’s registers havethe following values at the beginning of the cycle in which the above instructionword is fetched: R0 R1 R2 R3 R4 R5 R6 R8 R12 R31 0 2 4 6 13 10 12 16 24 31 a. What are the outputs of the sign-extend and the jump “Shift-Left-2” (near the topof the following Figure) for this instruction word? (Pic3) b. What are the values of ALU control unit’s inputs (ALUOp and Instruction[5-0])for this instruction? c. What is the new PC address after this instruction is executed? Highlight the paththrough which this value is determined. d. For the ALU and the two add units, what are their data input values? ALU Add (PC+4) Add…
Consider a HW ISA program P1 with the following Instruction Memory IM: Jamie wants to translate program P1 (except for the final HALT instruction) into a sequence of statements in a version of C with a 16-bit int type. Using the IM Fill in the rest of her program with assignments to variables named R2, R3, and R4 that represent the registers with these names in P1 and a while loop. int R0 = 0; int R1 = 1; int R2 = R0 + R0; // ...
For our simple 2-stage pipeline, we run a particular benchmark program and find that it has 19% conditional branches. An additional 4% are unconditional branches. What is the maximum number of the conditional branches that could be taken if we want to keep the CPI to 1.10 or less? what is the minimum percentage of branch delay slots that need to be filled with useful instructions in order to keep the CPI to 1.0135? I know other students have posted similar questions and they are answered, but those answers do not seem correct, so please do not copy from them
Consider the following portions of three different programs running at the same time on three processors in a symmetric multicore processor (SMP). Assume that before this code is run, W is 10, X= 50, Y=15, Z=5. Core 1: Total = W+ X;Core 2: Total = W - Y;Core 3: Total = W + Z; b) What are all the possible resulting values of Total? For each possible outcome, explain how we might arrive at those values. You will need to show all possible interleavings of instructions. c) How could you make the execution more deterministic so that only one set of values is possible?
In this exercise we examine in detail how an instruction is executed in a single-cycle datapath. Problems in this exercise refer to a clock cycle in which the processor fetches the following instruction word: 10101100100001010000000000010100 Assume that the data memory is all zeros and that the processor’s registers have the following values at the beginning of the cycle in which the above instruction word is fetched: R0 R1 R2 R3 R4 R5 R6 R8 R12 R31 0 1 -2 3 -4 5 -6 -8 -12 31 1. What are the outputs of the sign-extend and the jump “Shift-Left-2” (near the top of Figure 4.24) for this instruction word? 2. What are the values of ALU control unit’s inputs (ALUOp and Instruction operation) for this instruction? 3. What is the new PC address after this instruction is executed? Highlight the path through which this value is determined. 4. For the ALU and the two add units, what are their data input values? 5. What are the values of all inputs for the “Registers” unit?
17. Consider the following hypothetical instruction: SubMem R1, mem1, mem2 This instruction works as follows: \[ \mathrm{R} 1 \leftarrow \text { [mem1] - [mem2] } \] In a multi-cycle datapath implementation, this instruction will: a. Use the MDR twice b. Use the ALU once c. Use the "shift to left" unit twice d. None of the above Answer: B 18. Consider the following hypothetical instruction: Mems mem1, R1, mem2 This instruction works as follows: \[ \text { [mem1] } \leftarrow \mathrm{R} 1 \text { - [mem2] } \] One of the following is correct about this instruction: a. It will not need theBregister b. It will require priting into MDR twice c. It will require writing into the ALUout three times d. None of the above Answer: A 19. By comparing the hypothetical instructions given in Questions (17) and (18), if we run these instructions on the same processor, then one of the following is correct: a. Both instructions have the same CPI b. Mems executes faster than SubMem c. SubMem executes…

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