Draw the Output Waveforms: Analyze and draw the output waveforms for the following digital circuits, considering their control signal status (active-high or active-low). a. D latch with active-high enable signal. Clk D Q b. D latch with active-low enable signal. Clk D Q c. Falling edge-triggered D flip-flop. Clk D Q D D Q Clk E Q D D Q Clk E Q D D Q Clk

Consider a digital logic circuit with two diodes as shownin figure 1. The diodes D1 and D2 are ideal (i.e. Vy = 0). 12 D ov, out 10 D2 5V 50kO Figure 1 A digital logic circuit with two ideal diodes A. Complete the equivalent circuit below and determine the output voltage vout oV and v, = 5V. Verify the conduction states of diodes by finding the current through D, and the voltage across D, when vị = Note that the output voltage is the same when v, = 5V and v, = 0V. 12 D out 12 D2 5V 50k2 Complete the equivalent circuit below and determine the output voltage vout when vị = v2 = В. 5V. 1Ω D Qut 10 5V 50k2 B.

Draw a clock signal CLK with five 0-to-1 timing events, a nonzero setup time, tsu, and a nonzero hold time,th. Also draw one excitation input signal EI that follows the sequence 10110 and meets the setup and hold timerequirements. In the excitation input, the first bit in the sequence (1) occurs in time for the first clock timingevent, the second bit in the sequence (0) occurs in time for the second clock timing event, and so forth.