Given a system with separate instruction and data caches, suppose the frequency of data operations is 0.31. Given a HitTime of 1ns for each cache and a miss penalty of 50ns for each cache, calculate the average memory access time (in nsec). Assume that the miss rate for the data cache is 0.08 and the miss rate for the instruction cache is 0.04.Round your answer to two decimal places

Consider a CPU that operates with a data transfer rate of 30 Mbytes/s. The data is transferred byte-wise and the CPU has to transfer 30bytes of data, and the size of the Status register is 4 bytes. What is the total time needed to perform the data transfer?

For a computer with 56-bit physical addresses and a 8-way set associative cache of 64 KB where each cache line has the capacity of holding 32 words. Assume the word size is 3 and the architecture is byte-addressable. Answer the questions below: a.How many bits are needed for tag, index, word offset, and byte offs. Show your derivations and assumptions. b.What are the start and end physical addresses, in hex as discussed in class, for cache line 300? Cache line count starts from 0. c.What is the total size, in KB, of this cache? d.What is the tag value, in hex, of address 0xABCDEF98765432?

Assume a data bus is 16 bits wide. The data and address lines are multiplexed. If the bus runs at a speed of 300MHz, how long will it take to transfer 15MB over the bus?