In a smartphone, the length of the main memory address is 16-bits. Its L1 cache size is 2K-byte. This cache uses the LRU replacement algorithm and is organized as a 4-way set-associative cache with 64 bytes per cache line. Consider the memory as word addressable and the size of the word is 1 byte. i) How many lines are there in the cache? 11) How many sets are there in the cache? 111) Calculate the number of bits in each of the Tag, Set, and Word fields of the memory address. iv) When a program is dxecuted, the processor reads data sequentially from the following word addresses: 128H, 144H, 176H, 180H, 129H, 170H All the above addresses are shown in hexadecimal values. Assume that the cache is initially empty. For each of the above addresses, indicate whether the cache access will result in a hit or a miss. Justify your answer.

Computer Networking: A Top-Down Approach (7th Edition)
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Author:James Kurose, Keith Ross
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Chapter1: Computer Networks And The Internet
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In a smartphone, the length of the main memory address is 16-bits. Its L1
cache size is 2K-byte. This cache uses the LRU replacement algorithm and is organized
as a 4-way set-associative cache with 64 bytes per cache line. Consider the memory as
word addressable and the size of the word is 1 byte.
i) How many lines are there in the cache?
11) How many sets are there in the cache?
111) Calculate the number of bits in each of the Tag, Set, and Word fields of the memory
address.
iv) When a program is dxecuted, the processor reads data sequentially from the
following word addresses:
128H, 144H, 176H, 180H, 129H, 170H
All the above addresses are shown in hexadecimal values. Assume that the cache is
initially empty. For each of the above addresses, indicate whether the cache access
will result in a hit or a miss. Justify your answer.
Transcribed Image Text:In a smartphone, the length of the main memory address is 16-bits. Its L1 cache size is 2K-byte. This cache uses the LRU replacement algorithm and is organized as a 4-way set-associative cache with 64 bytes per cache line. Consider the memory as word addressable and the size of the word is 1 byte. i) How many lines are there in the cache? 11) How many sets are there in the cache? 111) Calculate the number of bits in each of the Tag, Set, and Word fields of the memory address. iv) When a program is dxecuted, the processor reads data sequentially from the following word addresses: 128H, 144H, 176H, 180H, 129H, 170H All the above addresses are shown in hexadecimal values. Assume that the cache is initially empty. For each of the above addresses, indicate whether the cache access will result in a hit or a miss. Justify your answer.
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