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Intel x86 processors are developed from 16-bit, 32-bit to 64-bit processors.
a. What is meant by an n-bit processor, n can be 8,16,32 or 64.
b. Explain the similarities and differences between Intel 16-bit, 32-bit and 64-bit processors.
c. Explain how a 64-bit register on Intel x86, can be accessed as a 32-bit, 16-bit and 8-bit register.
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- How does pipelining improve CPU efficiency? What’s the potential effect on pipelining’s efficiency when executing a conditional BRANCH instruction? What techniques can be used to make pipelining more efficient when executing conditional BRANCH instructions?Most Intel CPUs use the __________, in which each memory address is represented by two integers.Question 1 ( Why is it important for us to develop good designs in Computer Architecture? Give two reasons . In the design of a processor chip, suggest two aspects that could ----------to improved performance. Explain your answer. What is the performance implication of designing one microprocessor using RISC and the other one as CISC architecture in modern machines? Consider two machines where one is a uniprocessor and the other is a multiprocessor. Explain two techniques, one for each machine that are used to speed up execution of processes.
- The technologist's notion of Moore's Law is that the number of transistors per chip doubles approximately every 18 months. In the 1990s, Moore's Law started to be described as the doubling of microprocessor power every 18 months. Given this new variation of Moore’s Law, answer the following: After successfully completing your computer organization and architecture class, you have a brilliant idea for a new chip design that would make a processor six times faster than the fastest ones on the market today. Unfortunately, it will take you four and a half years to save the money, create the prototype, and build a finished product. If Moore’s Law holds, should you spend your money developing and producing your chip or invest in some other venture?We want to build a byte organized main memory of 8 GB for a 32-bit CPU architecture composed ofbyte organized memory modules of 30-bit address and 8-bit data buses each.a) Draw the interface of the main memory by clearly indicating the widths of the buses.b) How many memory modules would be necessary to build the memory system?c) Design the main memory internal organization built out of the above memory modules (usemultiplexers and/or decoders as needed) by clearly indicating the widths of the used bussesd) Can we use this memory system as RAM for the CPU in Problem 1? Explain your answer.The register content for an Intel 8086 microprocessor is as follows:CS = 1000H, DS = 2000H, SS = 5000H, SI = 2000H, DI = 4000HBX = 6783H, BP = 7000H, AX = 29FFH, CX = 8793H, DX = A297HCalculate the physical address of the memory where the operand is stored and the contents of the memory locations in each of the addresses shown below: a) MOV [SI], ALb) MOV [DI+6H], BXc) MOV [SI+BX–11], AXd) MOV [DI][BX]+28H, CXe) MOV [BP][SI]+17, DX
- 10. The register content for an Intel 8086 microprocessor is as follows:CS = 5000H, DS = 6000H, SS = 7000H, SI = 8000H, DI = 9000HBX = 4A1FH, BP = 3000H, AX = 3597H, CX = 19DAH, DX = 8B73HCalculate the physical address of the memory where the operand is stored and thecontents of the memory locations in each of the addresses shown below:a) MOV [BP + 58], AXb) MOV [SI][BX]+2FH, DXc) MOV [DI][SI]+49AH, DXIn the MC68000 microprocessor, the total memory address is 16 MB and it is based onaddress pins.i. Show how we could determine the total memory and give the number of addresspins.ii. As a design engineer, the manager asks you to design a newly developedMC68000x that is having 18/20/22 number of address pins. Determine the range ofmemory address that can be accessed by the newly developed microprocessor andillustrate it by using a simple illustration of a memory map.(a) Write the Assembly language instruction to move value 1234H into register BX.(b) Write the Assembly language instructions to add the values 16H and ABH. Place the result inregister AX.(c) No value can be moved directly into which registers ?(d) What is the largest hex value that can be moved into a 16-bit register ? Into an 8-bit register ? Whatare the decimal equivalents of these hex values ?
- 2. This question is about Digital Logic and Address DecodingA computer is being designed using a microprocessor with a 16-bit address bus (A0—A15, where A0 is the least significant bit). The 64K address space is to be split betweenand allocated to RAM, ROM and I/O hardware as follows:Address Range (hex) Contains Select Signal0x0000 — 0x1FFF Main RAM RAMCS0x8000 — 0x9FFF Video RAM VRAMCS0xB000 — 0xBFFF I/O hardware IOCS0xC000 — 0xCFFF BASIC ROM BROMCS0xF000 — 0xFFFF OS ROM OSROMCSThe rest of the address space is unused.Note: As with many computer systems, it its only necessary to decode addresses to sufficiently identify each of the sections above uniquely. It is acceptable for some parts to be decodeable by more than one address provided these extra addresses do not overlap any of the other specified address ranges. Using a combination of AND, OR and NOT gates and the signals (A12 — A15) that contain the top four bits of the address in binary form: a. Derive the equation for a logic…1) For a Pentium II descriptor that contains a base address of 0004B100H, a limit of 00FFFH, and G = 1, what starting and ending locations are addressed by this descriptor? 2) Code a descriptor that describes a memory segment that begins at location 0005CF00h and ends at location 00060EFFh. The memory segment is a data segment that grows upward in the memory system and can be written. The segment has a user level privilege (lowest) and has not been accessed. The descriptor is for an 80386 microprocessor.4.16.1 [5] <§4.5> What is the clock cycle time in a pipelined and non-pipelined processor? 4.16.2 [10] <§4.5> What is the total latency of an LDUR instruction in a pipelined and non-pipelined processor? 4.16.3 [10] <§4.5> If we can split one stage of the pipelined datapath into two new stages, each with half the latency of the original stage, which stage would you split and what is the new clock cycle time of the processor? 4.16.4 [10] <§4.5> Assuming there are no stalls or hazards, what is the utilization of the data memory? 4.16.5 [10] <§4.5> Assuming there are no stalls or hazards, what is the utilizationof the write-register port of the “Registers” unit?