c) Briefly explain immediate, direct, indirect and register addressing modes. =) What instructions usually are used to handle an I/O interrupt in a processor? ) What instructions typically are used to handle subroutine calls g) When comes to RISC v CISC comparison, how do they differ with respect to the kind of instructions they have? h) What is the difference between Programmed I/O and Interrupt I/O? Which one is more efficient?

c) Briefly explain immediate, direct, indirect and register addressing modes. =) What instructions usually are used to handle an I/O interrupt in a processor? ) What instructions typically are used to handle subroutine calls g) When comes to RISC v CISC comparison, how do they differ with respect to the kind of instructions they have? h) What is the difference between Programmed I/O and Interrupt I/O? Which one is more efficient?

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 2PE: If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the...

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If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the fetch cycle is 40% of the processor cycle time, what memory access speed is required to implement load operations with zero wait states and load operations with two wait states?
a)Analyse and elaborate the factors affecting the choice of instruction length in aprocessor. b)A processor is able to perform a variable length instruction. It can performTHREE (3) different instruction length modes as follows:• instructions with two 15-bit addresses and one 3-bit register number• instructions with one 15-bit address and one 3-bit register number• instructions with no addresses or registersDesign a variable-length opcode to allow all the instruction to be encoded in a 36-bit instruction. Justify your answer. c)Briefly define the following terms:(i) instruction-level parallelism(ii) true data dependency(iii) procedural dependency(iv) resource conflicts
12.In the following items, the characteristics of non-compliant RISC instruction systems are ( ).A. The length of the instruction is fixed, and the type of the instruction is small. B.The type of addressing mode is minimized, and the instruction function is as strong as possible.C. Increase the number of registers to minimize the number of accesses. D. Select the most frequently used simple instructions, and useful but not complex instructions.
Consider the following program in MARIE assembly language. a) Complete the table detailing the RTN for next 2 instructions only that will be executed including the content of registers PC, IR, MAR, MBR and AC in hexadecimal. Note the first instruction LOAD X is already filled. Note also that SKIPCOND instruction has no operands, therefore you can complete Fetch, decode and execute cycles only. b) Explain in one statement the task performed by this program?
6. Assume that two numbers: dividend and divisor are saved in memory address M1 and M2 respectively. Quotient and remainder should be saved in R1 and R2 respectively. Write assembly language instructions and then list microoperations for each instruction and list the control signals required to be activated for each microoperation. MBR is used as buffer for any register to register transfer operation. Signal Description: Control signals operation Comments C0 MAR to RAM (through address bus) C1 PC to MBR C2 PC to MAR C3 MBR to PC C4 MBR to IR C5 RAM to MBR C6 MBR to ALU C7 Accumulator to ALU C8 IR to MAR C9 ALU to Accumulator C10 MBR to Accumulator C11 Accumulator to MBR C12 MBR to RAM (through data bus) C13 IR to Control Unit C14 MBR to R1 C15 MBR to R2 C16 MBR to R3 C17 MBR to R4…
Assume that one 32-bit and two 16-bit microprocessors are to be interfaced to a system bus. The following details are given: All microprocessors have the hardware features necessary for any type of data transfer: programmed I/O, interrupt-driven IO, and DMA. All microprocessors have a 16-bit address bus. Two memory boards, each of 128 KBytes capacity, are interfaced with the bus. The designer wishes to use a shared memory that is as large as possible. The system bus supports a maximum of four interrupt lines and one DMA line. Make any other assumptions necessary, and do the following: a. Give the system bus specifications in terms of number and types of lines. b. Describe a possible protocol for communicating on the bus (i.e., read-write, interrupt, and DMA sequences). c. Explain how the aforementioned devices are interfaced to the system bus.
a. How many bits are needed for the opcode of memory unit with 24 bits per word and instruction set consists of 199 different operations? b. How many bits are left for the address part of the instruction?
We want to build a byte organized main memory of 8 GB for a 32-bit CPU architecture composed ofbyte organized memory modules of 30-bit address and 8-bit data buses each.a) Draw the interface of the main memory by clearly indicating the widths of the buses.b) How many memory modules would be necessary to build the memory system?c) Design the main memory internal organization built out of the above memory modules (usemultiplexers and/or decoders as needed) by clearly indicating the widths of the used bussesd) Can we use this memory system as RAM for the CPU in Problem 1? Explain your answer.
10. The register content for an Intel 8086 microprocessor is as follows:CS = 5000H, DS = 6000H, SS = 7000H, SI = 8000H, DI = 9000HBX = 4A1FH, BP = 3000H, AX = 3597H, CX = 19DAH, DX = 8B73HCalculate the physical address of the memory where the operand is stored and thecontents of the memory locations in each of the addresses shown below:a) MOV [BP + 58], AXb) MOV [SI][BX]+2FH, DXc) MOV [DI][SI]+49AH, DX
computer architecture Assume that the operation times of one add instruction for the major functional units are 325 ps for memory access, 185 ps for ALU operations and 125 ps for register file read/writes. Please fill the table first and perform the following a )What is the total cycle in single-cycle implementation? b )What is the total cycle in pipelining implementation? c) What is the total cycle in pipelining implementation if there are 5 million add instructions? d) What is the total cycle in pipelining implementation for 5 million add instructions, if the stages are balanced? e)What is the speed up of pipelining implementation over single-cycle implementation?
Design a CPU System that combines and connect memory system, ALU, registers and controlunit. The CPU MUST use a 16-bit instruction format where 4-bit for Opcode, 6-bit forOperand 1 and 6-bit for Operand 2 as shown below: The CPU should be able to perform the complete instruction cycle (fetch instruction (FI),decode instruction (DI), calculate operands (CO), fetch operands (FO), execute the instruction(EI), and write operand (WO). To verify the functionality of the CPU system, the studentshave to create test benches to demonstrate that the CPU is able to perform at least thecomputations as shown below: You are asked to draw the Flow Chart based on the information given above. The Flow Chart drawn must be accompanied by a brief description of it.
Suppose a machine has word length of 32 bits, and the CPU has 32 registers of 32 bits. Design an instruction system with 64 operations. (1) If it uses register addressing mode and the direct addressing mode in the instruction, what is the maximum main memory space that can be addressed? (2) What are the differences between the based index addressing and index addressing? (3) Introduce at least three of other addressing methods that can be used.