Q4/ B- answer the following questions : 1- In which T-state does the CPU sends the address to memory or I/0 and the ALE signal for demultiplexing 2- Which type of JMP instruction assembles if the distance is 005F H bytes 3- Direction flag is used with?
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- If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the fetch cycle is 40% of the processor cycle time, what memory access speed is required to implement load operations with zero wait states and load operations with two wait states?What is the name of the Intel technology that allows a processor to handle two threads at the same time?How does pipelining improve CPU efficiency? What’s the potential effect on pipelining’s efficiency when executing a conditional BRANCH instruction? What techniques can be used to make pipelining more efficient when executing conditional BRANCH instructions?
- The MSP430 can move/copy a byte or a word at a time using the instructions mov.b and mov.w respectively. In particular, the instructions mov.b &source_address, R4 mov.w &source_address, R4 copy the byte or word that resides at the given address (&source_address) to the given destination (the core register R4 in the CPU). Which of the following instructions are valid? (a) mov.b &0x1C03, R4 (b) mov.w &0x1C02, R4 (c) mov.b &0x1C00, R4 (d) mov.w &0x1C05, R4QUESTION 2 Discuss with examples the main difference between system programming and application programming and explain in your own words how each of these can be carried out in the computer system. With your knowledge in memory addressing modes and using the given opcodes LDA = 00 0000 0000 (00) 0 (x) What will be the content of the address loaded into the accumulator? b. With your knowledge in memory addressing mods and using the given opcodes STCH = OX54 Buffer = 1000 0101 0100 (00) 1 (x) 000 1000 0000 0000 () 011 0000 0000 0000 () What will be target address? Briefly explain the usage of the JSUB and RSUB instruction sets in an SIC architecture codingWhich memory address in Interrupt Vector Table (IVT) stores the higher byte of the segment part forthe beginning address of ISR that corresponds to ITC 15 H? Justify your answer with calculation. give diagram if needed
- 10. Q1 : What is an atomic instruction? Show that if the wait operation is not executed atomically, then mutual exclusion may be violated Q2: What is spinlock? Discuss the advantage and disadvantage of using spinlock. Why do you think Solaris, Linux, and Windows 2000 use spinlocks as a synchronization mechanism only on multiprocessor systems and not on single- processor systems?Please answer both questions a)There are 3 forms of Program Memory Addressing Modes: Direct, Relative and Indirect. Explain/Illustrate what happens to CS and IP registers if the JMP THERE instruction is stored at memory address 10000H (CS=1000H, IP=0000H) and the address of THERE is:(i) 10020H(ii) 30000H(b) Determine whether the JMP THERE instructions are SHORT, NEAR or FAR jump. Explain your answer.Q:Answer the following sentence with (True) or (False) and correct the false answer: 1. You can input data of size 16-bit through the fixed port. 2. In the maximum mode, the status signals S₁, S₂ and S3 are controlled by the bus controller. 3. HLDA is an output signal. 4. In 8086, when executing the instruction MOV AL, [SI+100D H] where SI-100AH, Ao=0 and BHE=1 5. When S, is 0, the TF is disabled.
- 33. Which one of the following is true with regard to a CPU having a single interrupt request line and single interrupt grant line…??i) Neither vectored nor multiple interrupting devices is possible.ii) Vectored interrupts is not possible but multiple interrupting devices is possible.iii) Vectored interrupts is possible and multiple interrupting devices is not possible.iv) Both vectored and multiple interrupting devices is possible. a. iii b. i,iv c. ii,iii d. iii,iv4. Memory and Addressing Modes The state of the CPU and memory is represeated by this diagram. _m Address | Value X [ | =] | S R [pc_[srooo | s Jsoueo] [Fag(p) [N [v[1]e o i [2]c] [vaive Jofo]1]ofofo]1]1] a) Value of A after execution of LDA #50D? b) Value of A after execution of LDA #S0F? €) Value of Y after execution of LDY $0D? ) Value of Y after LDY ${000F), X? ) Value of Y after LDY ($0F), X2 please show workings!1. Name all of the general purpose registers and some of their special functions. 2. How are the segment registers used to form a 20-bit address? 3. (a) If CS contains 03E0H and IP contains 1F20H, from what address is the next instruction fetched? (b) If SS contains 0400H and SP contains 3FFEH, where is the top of the stack located? (c) If a data segment deigns at address 24000H, what is the address of the last location in the segment? 4. Explain what the instruction array and data caches are used for. 5. What is the EU and BIU, and what purpose in the microcomputer? 6. Two memory locations, beginning at address 3000H, contain the bytes 34H and 12H. What is the word stored at location 3000H? See Figure 2.26 for details. Address 3000 Data 34 3001 12 Figure 2.26 For question 6 7. What is a physical address? What are the differences between the 8086 logical and physical memory maps? 8. May memory segments overlap? If so, what is the minimum number of overlapped bytes…
