Chapter 16, Problem 16.62P

(a)

To determine

To construct: The table for the state of each transistor.

To find: The output voltage $v_{O1}$ , $v_{O2}$ and $v_{O3}$ for the input logic state.

Answer to Problem 16.62P

The value of the output voltages is obtained and is shown in Table 2

Explanation of Solution

Calculation:

The given diagram is shown in Figure 1

  

The given table is shown in Table 1

Table 1

State	CLK	$v_X$	$v_Y$	$v_Z$
$1$	$0$	$0$	$0$	$0$
$2$	$1$	$1$	$1$	$1$
$3$	$0$	$0$	$0$	$0$
$4$	$1$	$0$	$1$	$1$
$5$	$0$	$0$	$0$	$0$
$6$	$1$	$1$	$0$	$1$

For state 1

The input clock signal input X, Y and Z are at logic zero and the logic function of the output voltage $v_{O1}$ is the compliment of the input voltage $v_X$ an is given by,

  $v_{O1}={\overline{v}}_X$   ....... (1).

Substitute $0$ for $v_X$ in the above equation.

  $\begin{array}{c}{v}_{O1}=\overline{0}\\ =1\end{array}$

From the circuit the NMOS device with the input $v_Y$ is in series with the parallel combination of the NMOS device of input $v_Z$ and the compliment $v_{o1}$ .

The expression for the logic function of the output voltage $v_{o2}$ is given by,

  $v_{O2}=\overline{v_Y\left({\overline{v}}_{O1}+v_Z\right)}$   ...... (2)

Substitute $1$ for $v_{O1}$ , $0$ for $v_Y$ and $0$ for $v_Z$ in the above equation.

  $\begin{array}{c}{v}_{O2}=\overline{0\left(\overline{1}+0\right)}\\ =1\end{array}$

The logic function of the output voltage $v_{O3}$ is the compliment of the output voltage $v_{O2}$ and is given by,

  $v_{O3}=\overline{v_{O2}}$   ...... (3)

Substitute $1$ for $v_{O2}$ in the above equation.

  $\begin{array}{c}{v}_{O3}=\overline{1}\\ =0\end{array}$

For state 2.

All the inputs are at logic 1.

Substitute $1$ for $v_X$ in equation (1)

  $\begin{array}{c}{v}_{O1}=\overline{1}\\ =0\end{array}$

Substitute $0$ for $v_{O1}$ , $1$ for $v_Y$ and $1$ for $v_Z$ in equation (2)

  $\begin{array}{c}{v}_{O2}=\overline{1\left(\overline{0}+1\right)}\\ =1\end{array}$

Substitute $0$ for $v_{O2}$ in equation (3)

  $\begin{array}{c}{v}_{O3}=\overline{0}\\ =1\end{array}$

For state 3.

All the inputs are at logic 0.

Substitute $0$ for $v_X$ in equation (1)

  $\begin{array}{c}{v}_{O1}=\overline{0}\\ =1\end{array}$

Substitute $1$ for $v_{O1}$ , $0$ for $v_Y$ and $0$ for $v_Z$ in equation (2)

  $\begin{array}{c}{v}_{O2}=\overline{0\left(\overline{1}+0\right)}\\ =1\end{array}$

Substitute $1$ for $v_{O2}$ in equation (3)

  $\begin{array}{c}{v}_{O3}=\overline{1}\\ =0\end{array}$

For state 4.

The input clock, $v_Y$ and the input $v_Z$ are at logic zero and the input $v_X$ is at logic zero.

Substitute $0$ for $v_X$ in equation (1)

  $\begin{array}{c}{v}_{O1}=\overline{0}\\ =1\end{array}$

Substitute $1$ for $v_{O1}$ , $1$ for $v_Y$ and $1$ for $v_Z$ in equation (2)

  $\begin{array}{c}{v}_{O2}=\overline{1\left(\overline{1}+1\right)}\\ =0\end{array}$

Substitute $0$ for $v_{O2}$ in equation (3)

  $\begin{array}{c}{v}_{O3}=\overline{0}\\ =1\end{array}$

For state 5.

All the inputs are at logic zero.

Substitute $0$ for $v_X$ in equation (1)

  $\begin{array}{c}{v}_{O1}=\overline{0}\\ =1\end{array}$

Substitute $1$ for $v_{O1}$ , $0$ for $v_Y$ and $0$ for $v_Z$ in equation (2)

  $\begin{array}{c}{v}_{O2}=\overline{0\left(\overline{1}+0\right)}\\ =1\end{array}$

Substitute $1$ for $v_{O2}$ in equation (3)

  $\begin{array}{c}{v}_{O3}=\overline{1}\\ =0\end{array}$

For state 6.

The input clock, $v_X$ and the input $v_Z$ are at logic zero and the input $v_Y$ is at logic zero.

Substitute $1$ for $v_X$ in equation (1)

  $\begin{array}{c}{v}_{O1}=\overline{1}\\ =0\end{array}$

Substitute $0$ for $v_{O1}$ , $0$ for $v_Y$ and $1$ for $v_Z$ in equation (2)

  $\begin{array}{c}{v}_{O2}=\overline{0\left(\overline{0}+1\right)}\\ =1\end{array}$

Substitute $1$ for $v_{O2}$ in equation (3)

  $\begin{array}{c}{v}_{O3}=\overline{1}\\ =0\end{array}$

The table for the state of the transistors and the output voltage is shown in table below.

The required table is shown in Table 2

Table 2

State	CLK	$v_X$	$v_Y$	$v_Z$	$v_{O1}$	$v_{O2}$	$v_{O3}$
$1$	$0$	$0$	$0$	$0$	$5\text{V}$	$5\text{V}$	$0\text{V}$
$2$	$1$	$1$	$1$	$1$	$0\text{V}$	$0\text{V}$	$5\text{V}$
$3$	$0$	$0$	$0$	$0$	$5\text{V}$	$5\text{V}$	$0\text{V}$
$4$	$1$	$0$	$1$	$1$	$5\text{V}$		$5\text{V}$
$5$	$0$	$0$	$0$	$0$	$5\text{V}$	$5\text{V}$	$0\text{V}$
$6$	$1$	$1$	$0$	$1$	$0\text{V}$	$5\text{V}$	$0\text{V}$

The table for the state of the transistor is shown below.

Conclusion:

Therefore, the value of the output voltages is obtained and is shown in Table 2

(b)

To determine

The logic function that the circuit implements.

Answer to Problem 16.62P

The logic that the circuit performs is $\left(v_X\text{OR}{v}_Z\right)\text{AND}{v}_Y$ .

Explanation of Solution

Calculation:

The expression for the output voltage $v_{O3}$ is given by,

  $v_{O3}={\overline{v}}_{O3}$

Substitute $\overline{v_Y\left({\overline{v}}_{O1}+v_Z\right)}$ for $v_{O2}$ in the above equation.

  $\begin{array}{c}{v}_{O3}=\overline{\overline{v_Y\left({\overline{v}}_{O1}+v_Z\right)}}\\ =\left(v_X+v_Z\right)v_Y\\ =\left(v_X\text{OR}{v}_Z\right)\text{AND}{v}_Y\end{array}$

Conclusion:

Therefore, the logic that the circuit performs is $\left(v_X\text{OR}{v}_Z\right)\text{AND}{v}_Y$ .