Chapter 5, Problem 15E

Explanation of Solution

Contribution of last-level cache misses:

Given is:

Machine contains 25% of the typical instruction mix

15% of loads miss in the last level of on-chip cache

120 cycle’s penalty to reach main memory

Determining the contribution of last-level cache misses to the average number of cycles per instruction is as follows:

$\begin{array}{c}\text{Average number of cycles per instruction = }(\begin{array}{c}\text{instruction mix }\times \\ \end{array}\end{array}$

Explanation of Solution

Effect on cycles per instruction:

Given is:

Machine contains 25% of the typical instruction mix

15% of loads miss in the last level of on-chip cache

120 cycle’s penalty to reach main memory

Off-chip (L3 or L4) caches satisfy 90% of the misses from the last-level on-chip at the penalty of 30 cycles.

Determining effect on cycles per instruction is as follows:

$\begin{array}{c}\text{Effect on cycles per instruction = }\left(\begin{array}{c}\text{instruction mix }\times \\ \text{load miss in the last level of on-chip cache }\times \\ \left(\left(\text{off-chip cache }\times \text{ new penalty}\right)+\left(\text{0}\text{.1 }\times \text{ old penalty}\right)\right)\end{array}\right)\\ \text{= 0}\end{array}$