Computer Systems: A Programmer's Perspective (3rd Edition)
3rd Edition
ISBN: 9780134092669
Author: Bryant, Randal E. Bryant, David R. O'Hallaron, David R., Randal E.; O'Hallaron, Bryant/O'hallaron
Publisher: PEARSON
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Chapter 9.3, Problem 9.2PP
Program Plan Intro
Page table entries (PTEs):
A page table is a collection of page table entries. In the virtual address space, each page has a page table entries at a fixed offset.
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I ONLY NEED 3 AND 4
Suppose memory has 256KB, OS use low address 20KB, there is one program sequence:
Prog1 request 80KB, prog2 request 16KB,
Prog3 request 140KB
Prog1 finish, Prog3 finish;
Prog4 request 80KB, Prog5 request 120kb
Use first match and best match to deal with this sequence
(from high address when allocated)
(1)Draw allocation state when prog1,2,3 are loaded into memory?
(2)Draw allocation state when prog1, 3 finish?
(3)use these two algorithms to draw the structure of free queue after prog1 , 3 finish
(4) Which algorithm is suitable for this sequence ? Describe the allocation process?
1. Develop a mathematical model for measuring performance based on overall memory
access time with a neat diagram for the following memory design and derive the
formula to calculate the Overall Memory Access Time.
Main Memory : 1
Internal Cache : 1
External Cache: 1
Register S and Register B have fastest access time:
Data Search order [ Registers – Internal Cache – External Cache – Memory]
[Hint: Register access time is considered negligible]
This problem studies the effect of changing page sizes in a demand paging system.
The following sequence of requests for program words is taken from a 460-word program: 10, 11, 104, 170, 73, 309, 185, 245, 246, 434, 458, 364. Main memory can hold a total of 200 words for this program, and the page frame size will match the size of the pages into which the program has been divided. Calculate the page numbers according to the page size and divide by the page size to get the page number. The number of page frames in memory is the total number, 200, divided by the page size. For example, in problem (a) the page size is 100, which means that requests 10 and 11 are on Page 0, and requests 104 and 170 are on Page 1. The number of page frames is two.
a. Find the success frequency for the request list using a FIFO replacement algorithm and a page size of 100 words (there are two page frames).
b. Find the success frequency for the request list using a FIFO replacement algorithm and a page…
Chapter 9 Solutions
Computer Systems: A Programmer's Perspective (3rd Edition)
Ch. 9.2 - Prob. 9.1PPCh. 9.3 - Prob. 9.2PPCh. 9.6 - Prob. 9.3PPCh. 9.6 - Prob. 9.4PPCh. 9.8 - Practice Problem 9.5 (solution page 882) Write a C...Ch. 9.9 - Prob. 9.6PPCh. 9.9 - Prob. 9.7PPCh. 9.9 - Prob. 9.8PPCh. 9.9 - Prob. 9.9PPCh. 9.9 - Prob. 9.10PP
Ch. 9 - Prob. 9.11HWCh. 9 - Repeat Problem 9.11 for the following address....Ch. 9 - Repeat Problem 9.11 for the following address....Ch. 9 - Given an input file hello.txt that consists of the...Ch. 9 - Determine the block sizes and header values that...Ch. 9 - Prob. 9.16HWCh. 9 - Prob. 9.17HWCh. 9 - Prob. 9.18HWCh. 9 - Prob. 9.19HWCh. 9 - Write your own version of malloc and free, and...
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- Answer only 3 and 4 Suppose memory has 256KB, OS use low address 20KB, there is one program sequence: (20) • Prog1 request 80KB, prog2 request 16KB, • Prog3 request 140KB • Prog1 finish, Prog3 finish; • Prog4 request 80KB, Prog5 request 120kb • Use first match and best match to deal with this sequence • (from high address when allocated) • (1)Draw allocation state when prog1,2,3 are loaded into memory? • (2)Draw allocation state when prog1, 3 finish? • (3)use these two algorithms to draw the structure of free queue after prog1 , 3 finish(draw the allocation descriptor information,) • (4) Which algorithm is suitable for this sequence ? Describe the allocation process?arrow_forwardThis problem studies the effect of changing page sizes in a demand paging system. The following sequence of requests for program words is taken from a 460-word program: 10, 11, 104, 170, 73, 309, 185,245,246,434,458, and 364. Main memory can hold a total of 200 words for this program, and the page frame size will match the size of the pages into which the program has been divided. Calculate the page numbers according to the page size; divide by the page size, and the quotient gives the page number. The number of page frames in memory is the total number, 200, divided by the page size. For example, in problem (a) the page size is 100, which means that requests 10 and 11 are on Page 0, and requests 104 and 170 are on Page 1. Therefore, the number of page frames is two. a.) Find the success frequency for the request list using a FIFO replacement Algorithm and a page size of 100 words (there are two page frames). b.) Find the success frequency for the request list using a FIFO…arrow_forward1. We wish to compare the performance of two different machines: M1 and M2. The following measurements have been made on these machines: Program Time on M1 Time on M2 1 10 seconds 5 seconds 2 3 seconds 4 seconds Which machine is faster for each program, and by how much? 2. For M1 and M2 of problem 1, the following additional measurements are made:. Find the instruction execution rate (instructions per second) for each machine when running program 1. Program Instructions executed on M1 Instructions executed on M2 1 200 x 106 160 x 106 3. For M1 and M2 of problem 1, if the clock rates are 200 MHz and 300 MHz, respectively, find the CPI for program 1 on both machines using the data provided in problems 1 and 2. 4. You are going to enhance a machine, and there are two possible improvements: either make multiply instructions run four times faster than before or make memory access instructions run two times faster than before. You…arrow_forward
- (15pt) Assume that instruction cache miss rate is 2%, data cache miss rate is 10%, CPI (clock cycle per instruction) is 2 without any memory stall, and miss penalty is 100 cycles. In addition, assume that the frequency of loads/stores is 30%. (a) Compute CPI with memory stall. (b) When CPI without any memory stall becomes 1, compute CPI with memory stall. (c) If the CPU clock rate is doubled with the same memory when CPI without memory stall is 2, compute CPI with memory stall.arrow_forwardSection 1.0 cites as a pitfall the utilization of a subset of the performace equation as a performance metric. To illustrate this, consider the following two processors. P1 has a clock rate of 4GHz, average CPI of 0.9, and requires the execution of 5.0E9 instructions. P2 has a clock rate of 3GHz, an average CPI of 0.75, and requires the execution of 1.0E9 instructions. (1) A common fallacy is to use MIPS to compare the performace of two different processors, and consider that the processor with the largest MIPS has the largest performance. Check if this is true for P1 and P2. (2) Another common performace figure is MFLOPS, defined as MFLOPS = No. FP operations / (execution time x 1E6) but this figure has the same problems as MIPS. Assume that 40% of the instructions executed on both P1 and P2 are floating-point instructions. Find the MFLOPS figures for the processors.arrow_forwardQ 1 Computer Science Theory and Fundamentals of Operating Systems: Reference String: 7,6,8,2,6,3,6,4,2,3,6,3,2,8,2,6,8,7,6,8 How many page faults will occur if the program has three page-frames available to it and use Optimal replacement?arrow_forward
- 4.22 [5] <§4.5> Consider the fragment of LEGv8 assembly below: STUR X16, [X6, #12] LDUR X16, [X6, #8] SUB X7, X5, X4 CBZ X7, Label ADD X5, X1, X4 SUB X5, X15, X4 Suppose we modify the pipeline so that it has only one memory (that handles both instructions and data). In this case, there will be a structural hazard every time a program needs to fetch an instruction during the same cycle in which another instruction accesses data. 4.22.1 [5] <§4.5> Draw a pipeline diagram to show were the code above will stall. 4.22.2 [5] <§4.5> In general, is it possible to reduce the number of stalls/NOPs resulting from this structural hazard by reordering code? 4.22.3 [5] <§4.5> Must this structural hazard be handled in hardware? We have seen that data hazards can be eliminated by adding NOPs to the code. Can you do the same with this structural hazard? If so, explain how. If not, explain why not. 4.22.4 [5] <§4.5> Approximately how many stalls would you expect this…arrow_forward4.19.16: [5] <COD §4.6>. In this exercise, we examine how pipelining affects the clock cycle time of the processor. Problems in this exercise assume that individual stages of the datapath have the following latencies: Also, assume that instructions executed by the processor are broken down as follows: (a) What is the clock cycle time in a pipelined and non-pipelined processor? (b) What is the total latency of an lw instruction in a pipelined and non-pipelined processor? (c) If we can split one stage of the pipelined datapath into two new stages, each with half the latency of the original stage, which stage would you split and what is the new clock cycle time of the processor? (d) Assuming there are no stalls or hazards, what is the utilization of the data memory? (e) Assuming there are no stalls or hazards, what is the utilization of the write-register port of the "Registers" unit? No hand written and fast answer with explanationarrow_forward(Practice) Although the total number of bytes varies from computer to computer, memory sizes of millions and billions of bytes are common. In computer language, the letter M representsthe number 1,048,576, which is 2 raised to the 20th power, and G represents 1,073,741,824, which is 2 raised to the 30th power. Therefore, a memory size of 4 MB is really 4 times 1,048,576 (4,194,304 bytes), and a memory size of 2 GB is really 2 times 1,073,741,824 (2,147,483,648 bytes). Using this information, calculate the actual number of bytes in the following: a. A memory containing 512 MB b. A memory consisting of 512 MB words, where each word consists of 2 bytes c. A memory consisting of 512 MB words, where each word consists of 4 bytes d. A thumb drive that specifies 2 GB e. A disk that specifies 4 GB f. A disk that specifies 8 GBarrow_forward
- I am trying to better understand memory access in computers, please answer the sample question below. Assume that the page table can held in registers of the MMU. It takes 8 ms (milliseconds)to service a page fault if there is an empty frame or if the replaced page is not altered, and20 ms if the replaced page is altered. Memory access time is 100 ns (nanoseconds). It has been empirically measured that the page to be replaced is altered 75% of the time.Obtain the maximum probability of page fault for an effective memory access time ≤ 200ns.arrow_forward4.18 [5] <COD §4.5> Assume that X1 is initialized to 11 and X2 is initialized to 22. Suppose you executed the code below on a version of the pipeline from COD Section 4.5 (An overview of pipelining) that does not handle data hazards (i.e., the programmer is responsible for addressing data hazards by inserting NOP instructions where necessary). What would the final values of registers X3 and X4 be? ADDI X1, X2, #5 ADD X3, X1, X2 ADDI X4, X1, #15arrow_forwardNO PLAGARISM Assume that a main memory with only 4 frames each of 16 bytes is initially empty. The CPU generates the following sequence of virtual addresses and uses the Optimal Page replacement policy. 0,4,8,20,24,36,44,12,68,72,80,84,28,32,88,92 Your task is to find out the followings: a. How many page faults does this sequence cause? b. What are the page numbers of the pages which are present in the main memory at the end of the sequence? Assume that it is a byte addressable system.arrow_forward
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