A.
Virtual address:
Virtual page number (VPN) and virtual page offset (VPO) are the two components of virtual address. Virtual address is “14 bits” format.
B.
The page size (P) is 64bytes; using the page size find the number of bits in VPN.
The formula for page size as follows:
Substitute “P = 64” in the above formula
Therefore, the “p” value represents virtual page offset (VPO) and physical page offset (PPO).
Number of bits in VPN is calculated as follows:
n = 14
p = 6
The VPN has additional two more components. They are TLB tag (TLBT) and TLB index (TLBI). The TLB is “4 ways” associative with “16” entries totally. Using the TLB find the value of TLBI and TLBT.
The formula for TLB as follows:
Substitute “T = 4” in the above formula
Therefore, the “t” value represents TLBI.
TLBI and TLBT are calculated as follows:
The “t” value represents TLBI. Therefore, the value of TLBI is “2”.
TLBI = 2
VPN = 8
Therefore, the value of TLBT is “6”.
C.
Physical address:
Physical page number (PPN) and physical page offset (PPO) are the two components of physical address. Physical address is “12 bits” format. The physical page offset (PPO) is identical to the virtual page offset (VPO).
D.
The physical address has additional three more components. They are Byte offset within cache block (CO), Cache index (CI) and Cache tag (CT).
Want to see the full answer?
Check out a sample textbook solutionChapter 9 Solutions
Computer Systems: A Programmer's Perspective (3rd Edition)
- 4.22 [5] <§4.5> Consider the fragment of LEGv8 assembly below: STUR X16, [X6, #12] LDUR X16, [X6, #8] SUB X7, X5, X4 CBZ X7, Label ADD X5, X1, X4 SUB X5, X15, X4 Suppose we modify the pipeline so that it has only one memory (that handles both instructions and data). In this case, there will be a structural hazard every time a program needs to fetch an instruction during the same cycle in which another instruction accesses data. 4.22.1 [5] <§4.5> Draw a pipeline diagram to show were the code above will stall. 4.22.2 [5] <§4.5> In general, is it possible to reduce the number of stalls/NOPs resulting from this structural hazard by reordering code? 4.22.3 [5] <§4.5> Must this structural hazard be handled in hardware? We have seen that data hazards can be eliminated by adding NOPs to the code. Can you do the same with this structural hazard? If so, explain how. If not, explain why not. 4.22.4 [5] <§4.5> Approximately how many stalls would you expect this…arrow_forwardDue: Jan 4 Assignment 1 Compare performance for single-cycle, multicycle, and pipelined datapaths vy calculating execution time for each using the gcc instruction mixassume 2 ns for memory access, 2 ns for ALU operation, 1 ns for register read or writeassume gcc instruction mix 23% loads, 13% stores, 19% branches, 2% jumps, 43% ALUfor pipelined execution assume50% of the loads are followed immediately by an instruction that uses the result of the load25% of branches are mispredictedbranch delay on misprediction is 1 clock cyclejumps always incur 1 clock cycle delay so their average time is 2 clock cyclesarrow_forwardSection 1.0 cites as a pitfall the utilization of a subset of the performace equation as a performance metric. To illustrate this, consider the following two processors. P1 has a clock rate of 4GHz, average CPI of 0.9, and requires the execution of 5.0E9 instructions. P2 has a clock rate of 3GHz, an average CPI of 0.75, and requires the execution of 1.0E9 instructions. (1) A common fallacy is to use MIPS to compare the performace of two different processors, and consider that the processor with the largest MIPS has the largest performance. Check if this is true for P1 and P2. (2) Another common performace figure is MFLOPS, defined as MFLOPS = No. FP operations / (execution time x 1E6) but this figure has the same problems as MIPS. Assume that 40% of the instructions executed on both P1 and P2 are floating-point instructions. Find the MFLOPS figures for the processors.arrow_forward
- Problem: Assume a computer design problem having following parameters:Main memory: 128KB, 4-way Set-Associative mapped cache, Cache size: 1KB,Block size: 8 Bytes. Computer program accesses (in order) memory locations:137, 138, 169, 170, 1203, 1205.(i) What is the hit ratio?(ii) What are the final cache contents?Assume that the cache is empty at the beginning.arrow_forwardAnswer only 3 and 4 Suppose memory has 256KB, OS use low address 20KB, there is one program sequence: (20) • Prog1 request 80KB, prog2 request 16KB, • Prog3 request 140KB • Prog1 finish, Prog3 finish; • Prog4 request 80KB, Prog5 request 120kb • Use first match and best match to deal with this sequence • (from high address when allocated) • (1)Draw allocation state when prog1,2,3 are loaded into memory? • (2)Draw allocation state when prog1, 3 finish? • (3)use these two algorithms to draw the structure of free queue after prog1 , 3 finish(draw the allocation descriptor information,) • (4) Which algorithm is suitable for this sequence ? Describe the allocation process?arrow_forward4.18 [5] <COD §4.5> Assume that X1 is initialized to 11 and X2 is initialized to 22. Suppose you executed the code below on a version of the pipeline from COD Section 4.5 (An overview of pipelining) that does not handle data hazards (i.e., the programmer is responsible for addressing data hazards by inserting NOP instructions where necessary). What would the final values of registers X3 and X4 be? ADDI X1, X2, #5 ADD X3, X1, X2 ADDI X4, X1, #15arrow_forward
- <5.3> Caches are important to providing a high-performance memory hierarchy to processors. Below is a list of 32-bit hexadecimal memory addresses, given as byte addresses. 74, A0, 78, 38C, AC, 84, 88, 8C, 7C, 34, 38, 13C, 388, 18C For each of these references, identify the index and the tag, given a three-way set associative cache with two word blocks and a total of 24 words. List if each reference is a hit or a miss, assuming the cache is initially empty and show every entry to the cache, including the tag value and the addresses of all data items stored. Use hexadecimal or binary, whichever is easier.arrow_forwardQ-11: Assume a Computer design problem having following parameters: Main memory: 256 bytes, Direct mapped cache, Cache size: 4 lines, Block size: 4 bytes. Computer program accesses (in order) memory locations: F5, 53, 1C, 8A, 8B, 8C, E4, E5.What are the final cache contents?arrow_forward(15pt) Assume that instruction cache miss rate is 2%, data cache miss rate is 10%, CPI (clock cycle per instruction) is 2 without any memory stall, and miss penalty is 100 cycles. In addition, assume that the frequency of loads/stores is 30%. (a) Compute CPI with memory stall. (b) When CPI without any memory stall becomes 1, compute CPI with memory stall. (c) If the CPU clock rate is doubled with the same memory when CPI without memory stall is 2, compute CPI with memory stall.arrow_forward
- Question no 07: Write C Program Code to simulate Worst-Fit memory management Algorithm for the following Process. Number of Blocks: 6 (B1=6, B2=8, B3=10, B4=15, B5=20, B6=4) Number of Process: 5 (P1=1, P2=12, P3=17, P4=10, P5=6)arrow_forwardQuestion 1 Consider the size of main memory as 32 Bytes and the size of cache memory as 8 Bytes. Implement the Set-Associative mapping technique. Do the following: a) Find the number of bits to address 32 bytes in main memory b) Write the formula to map block of main memory to set of cache memory c) Find the block size, line size, set size, tag size d) Draw the figure to show the distribution of main memory in desired blocks containing bytes e) Draw the figure to show the distribution of cache memory in desired lines containing tag numbers, respective blocks, and byte numbers f) Show the tag allocation for each set (and line) of cache memoryarrow_forward(Practice) a. Using Figure 2.14 and assuming the variable name rate is assigned to the byte at memory address 159, determine the addresses corresponding to each variable declared in the following statements. Also, fill in the correct number of bytes with the initialization data included in the declaration statements. (Use letters for the characters, not the computer codes that would actually be stored.) floatrate; charch1=M,ch2=E,ch3=L,ch4=T; doubletaxes; intnum,count=0; b. Repeat Exercise 9a, but substitute the actual byte patterns that a computer using the ASCII code would use to store characters in the variables ch1, ch2, ch3, and ch4. (Hint: Use Appendix B.)arrow_forward
- C++ for Engineers and ScientistsComputer ScienceISBN:9781133187844Author:Bronson, Gary J.Publisher:Course Technology Ptr