Design a four-bit binary input (W3W2W1W0) priority encoder using necessary gates, with priority of the inputs given in the following table (input wo having the highest priority and input w3 having the lowest priority). Inputs Outputs W3 W2 W1 Wo ут yo Ꮓ 0 0 0 0 X X 0 1 0 0 0 0 0 1 X 1 0 0 0 1 1 X X 1 0 1 0 X X X 1 1 1 1

Create a complete analysis table for the circuit by finding the logic leveis present at each gate output for each of the 16 possible input combinations.

Design a combinational circuit that takes 3-bit pattern as input and outputs binary code of bit position of the first 1' in the pattern reading from MSB (2nd position) to LSB (0th position).An additional output variable V is required along with binary code to indicate that the binary code is valid or note i.e., if the input pattern is '000' then the output V should be '0' to indicate that the binary code is not indicating the bit position of first 1' and we don't care about the binary code if V = 0. Design the required circuit using dual 4x1 MUXS and minimum additional logic.Available resources along with dual 4x1 MUXS are NOT gates, 2-input(AND, OR, NAND, NOR) gates.

I need solution details in 30 minutes