Microelectronics: Circuit Analysis and Design
Microelectronics: Circuit Analysis and Design
4th Edition
ISBN: 9780073380643
Author: Donald A. Neamen
Publisher: McGraw-Hill Companies, The
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Chapter 14, Problem 14.55P

a.

To determine

Worst case output voltage for given circuit.

a.

Expert Solution
Check Mark

Answer to Problem 14.55P

The worst case output voltage is

  vo=9mV

Explanation of Solution

Given:

The given circuit is shown below.

  Microelectronics: Circuit Analysis and Design, Chapter 14, Problem 14.55P , additional homework tip  1

Input offset voltage V0S=2mV at T=25°C

Average input bias current IB=500nA

Input offset current IOS=100nA

  V0S=2mV at T=25°C

Calculation:

On applying V0S for both op-amp, the output voltage v0 due to input offset voltage effect as shown below.

  Microelectronics: Circuit Analysis and Design, Chapter 14, Problem 14.55P , additional homework tip  2

For given circuit VY=VOS

For an op-amp VY=VX

Then, VX=VOS

Now, KCL at input nodes:

  VXR1+VXvoR2=0R2VX+R1(VXvo)R1R2=0R2VX+R1(VXvo)=0(R1+R2)VX=R1vovo=(R1+R2R1)VXvo=(1+R2R1)VXvo=(1+R2R1)VOS.....(1)

For op-amp circuit

  R2=R1=50kΩR3=25kΩ

Now, output voltage due to input bias current and input offset current is,

  vo=R2IOSvo=50×103×100×109vo=5mV

Due to offset voltage,

From equation (1)

  vo=(1+50k50k)×2×103vo=2×2×103vo=4mV

So, the worst case output voltage for the circuit will be,

  vo=4mV+5mVvo=9mV

b.

To determine

Worst case output voltage for given circuit.

b.

Expert Solution
Check Mark

Answer to Problem 14.55P

The worst case output voltage is

  vo=1.0815V

Explanation of Solution

Given:

The given circuit is shown below.

  Microelectronics: Circuit Analysis and Design, Chapter 14, Problem 14.55P , additional homework tip  3

Input offset voltage V0S=2mV at T=25°C

Average input bias current IB=500nA

Input offset current IOS=100nA

  V0S=2mV at T=25°C

Calculation:

Consider the circuit shwon below.

  Microelectronics: Circuit Analysis and Design, Chapter 14, Problem 14.55P , additional homework tip  4

Apply KCL at non-inverting terminal

  VYR3+IB2=0VY=IB2R3

For op-amp VX=VY

So, VX=IB2R3.....(2)

Now, KCL at inverting terminal,

  VXR1+VXvoR2+IB1=0VX(1R1+1R3)voR2+IB1=0voR2=VX(1R1+1R3)+IB1vo=VX(R2R1+R2R3)+IB1R2

Putting VX from (1)vo=(IB2R3)(R2R1+R2R3)+IB1R2vo=IB1R2IB2R3(R2R1+1).....(3)

As,

  IB=IB1+IB22IB1+IB2=2IBIB1+IB2=2×500×109IB1+IB2=1000×109.....(4)

And

  IOS=|IB1IB2|IB1IB2=±IOSIB1IB2=±100×109....(5)

Adding (4) and (5)

  IB1+IB2+IB1IB2=1000×109±100×1092IB1=1000×109±100×109IB1=1100×1092or900×1092IB1=550×109or450×109

From (4)

  IB2=1000×109IB1

For IB1=550nA

  IB2=1000×109550nIB2=450nA

For IB1=450nA

  IB2=1000×109450nIB2=550nA

For the circuit

  R2=R1=50kΩR3=1MΩ

If offset voltage is negative, then from (1)

  vo=(1+50k50k)×(2×103)vo=2×2×103vo=4mV

Let IB1=450nA and IB2=550nA due to input bias current and input offset current

Putting IB1,IB2 and resistance values in (3)vo=(450×109×50×103)550×109×1×106(50k50k+1)vo=(0.0225)0.55(2)vo=1.0775V

So, the worst case output voltage for circuit is

  vo=4×1031.0775vo=1.0815V

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Chapter 14 Solutions

Microelectronics: Circuit Analysis and Design

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