T4

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Swinburne University of Technology *

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EEE20001

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Electrical Engineering

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Oct 30, 2023

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pdf

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Digital Electronics - Tutorial 10 of 46 Tutorial 4 Solution Q1) state A B C FF inputs J A K A J B K B Next state A + B + C + 0 0 0 0 1 1 1 0 0 1 0 0 0 1 0 1 1 1 1 0 1 1 0 1 0 1 1 1 1 1 1 0 1 0 1 1 1 1 1 1 0 1 0 0 1 0 0 0 1 0 1 0 0 0 0 1 0 1 0 1 0 1 1 0 0 1 1 1 0 1 1 0 1 1 0 0 1 1 1 1 1 1 0 1 0 0 0 0 Q2) state A B C Next state A + B + C + 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 1 0 1 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 0 1 1 1 1 1 1 0 1 1 Q3) Basically have an AND-gate at the T-input of the each FF. The AND-gates become wider as you move from LSB to MSB. Bit # Equation 0 1 1 C 0 2 C 1 C 0 3 C 2 C 1 C 0 4 C 3 C 2 C 1 C 0 5 C 4 C 3 C 2 C 1 C 0 To add a count enable input just add an extra input to each AND-gate which is connected to CEN. Q4) S 1 S 0 O 0 0 I 0 0 1 I 1 1 0 I 2 1 1 I 2 Q5) a) 'HC138 + 2-input OR-gate connected to O 0 and O 2 . Note: we are given the maxterms but we use the minterms. (Note ‘HC138 has active-low outputs so we actually use NAND gates). b) 'HC138 + 3-input OR-gate connected to O 2 , O 3 and O 7 . (Actually NANDs are used) 000 010 101 001 011 100 110 111 000 100 110 111 011 001 010 101 I 0 I 1 I 2 O S 1 S 0
Digital Electronics - Tutorial 11 of 46 F(a,b,c) = Σ m(2,3,7) Using the de-mux to create the above function would result in the individual creation of each of the minterms as shown at left. There would be possible hazards for the two transitions shown. Q6) The CET input and TC output allow us to implement a distributed AND-gate that is equivalent to the AND-gates of Q3) . Just connect the TC output of one 'HC161 to the CET input of the next from LSB to MSB. The CEP inputs can be connected together to act as a global count enable for the entire counter. Q7) F(a,b,c,d) = ab+ad+bd’+a’b’c a b c d F (a,b,c,d) Di 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 1 0 0 1 1 1 0 1 0 0 1 d’ 0 1 0 1 0 0 1 1 0 1 d’ 0 1 1 1 0 1 0 0 0 0 d 1 0 0 1 1 1 0 1 0 0 d 1 0 1 1 1 1 1 0 0 1 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 a b 01 11 10 1 0 c 00 a b c 1 1 1 1 1 1 1 1 1 1 a b 01 11 10 10 11 01 00 c d 00 a b c d 74HC151 0 D 0 1 D 1 D 2 D 3 d D 4 D 5 1 D 6 1 D 7 a S 2 b S 1 c S 0 O F(a,b,c,d) E 0 O F’(a,b,c,d) d'
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