Question 2: You are on the design team for a new processor. The clock of the processor runs at 200 MHz. The following table gives number of instruction for a Program A, as well as CPI, the instructions take, for the different classes of instructions. Турe Number of instructions CPI, ALU 50 Load 20 5 Store 10 Branch 20 a. Calculate the CPI for a Program A? b. Calculate the Execution time? 3. 2)

Question 2: You are on the design team for a new processor. The clock of the processor runs at 200 MHz. The following table gives number of instruction for a Program A, as well as CPI, the instructions take, for the different classes of instructions. Турe Number of instructions CPI, ALU 50 Load 20 5 Store 10 Branch 20 a. Calculate the CPI for a Program A? b. Calculate the Execution time? 3. 2)

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 4PE

See similar textbooks

Similar questions

How does pipelining improve CPU efficiency? What’s the potential effect on pipelining’s efficiency when executing a conditional BRANCH instruction? What techniques can be used to make pipelining more efficient when executing conditional BRANCH instructions?
8. For a single cycle processor, the instruction breakdown of a program is listed as following. add 20% addi 20% not 0% beq 25% Iw SW 25% 10% What is the percentage of instructions that will use the output of sign extend circuit-module? a. b. What is sign extend circuit-module doing when its output is not needed for current instruction?
The CPU design team is designing an instruction set with three classes of instructions. Parameters are given in the following table. Consider a program with 65% ALU instructions, 25% memory access instructions, and 10% control instructions. What is the average CPI for this CPU? Clock Rate 4GHz CPI for ALU Inst. 6 CPI for Memory Inst. 8 CPI for Control Inst. 2
Explain what you mean by "pipelining" in the context of improving processor speed, and then determine how many cycles it will take to run five instructions assuming each part of the machine requires one cycle. First, we'll look at the situation a) without pipelining and b) with pipelining. There are four ways to do this: a, b, c, and d, all of which include pipelining.
Question 5 • What are the actions involved during instruction execution? Explain the Fetch cycle or CPU cycle with a proper diagram. Full explain this question and text typing work only thanks
dont give existing answers surely downvote (a) A processor with a clock cycle time of 0.5 nanoseconds has a CPI of 4 for a particular program. What is the MIPS rating for this program? (b) A program is run on a system with two types of machine language instructions: type A instructions each require 3 clock cycles, while type B instructions each require 1 clock cycle. If 100 million type A instructions and 400 million type B instructions are executed, what is the CPI for this program? (c) For a particular program as run on a particular system, the CPU execution time is 1 second, the CPI is 4, and 750 million instructions were executed. What is the clock rate as measured in GHz?
A benchmark program to evaluate the performance of a processor spends 80% of its time on floating-point commands and 20% on non-floating point commands. A design team wants to obtain an overall speedup of 40% over the existing run time of this benchmark program by speeding up ONLY the non-floating point commands. What should be the ratio of the non-floating point commands new runtime to that of its old runtime? Select the best answer. This is a trick question! In this scenario, it is impossible to speed up only the non-floating point commands to obtain an overall 40% speedup! 2 0.5 2.5
You must show all work for every problem that requires it. The point values for problems may be changed at the professor's discretion. Read each question carefully and follow the instructions. A computer hardware as the following latency for its instructions in Pico seconds: Type Instruction Memory Register Read ALU Operation Data Memory Register Write Total R-Format 250 150 200 0 20 620 lw 250 150 200 250 20 870 sw 250 150 200 250 0 850 beq 250 150 200 0 0 600 J 250 0 0 0 0 250 For a single-cycle implementation what Clock Rate does the machine needs to operate at? For a multi-cycle implementation what Clock Rate does the machine needs to operate at? Provide the type, assembly language instruction and binary representation of instructions described by the following MIPS fields: Op=0x0, rs=3, rt=2, rd=3, shamt=0, funct=34 Op=0x23, rs=3, rt=1, const=0x4 In the snippet of assembly code below, how many times is…
You are designing a floating point coprocessor which will execute floating point instructions 5 times as fast as the regular processor with zero overhead. Given a workload that contains 25% floating point instructions, what is the speedup achieved by adding the coprocessor to the system? Please give the speedup with exact precision.
Stella designs a 3 GHz processor where two important programs, A and B, take one second each to execute. Each program has a CPI of 1.5. Sam is tasked with designing the company's next-generation processor and she comes up with an idea that improves the CPI of A to 1.25 and the CPI of B to 1. But the processor can only be implemented with a cycle time of 0.5 ns. Does Sam's new processor out-perform Stella's processor on program A? How about on program B?
The ISA of a processor has four classes of instructions: arithmetic, store, load and branch with CPI 2, 4, 4 and 1 respectively. Assume a program composed by 261 arithmetic operations, 829 stores, 262 loads and 130 branches. What is the execution time of the program in a 1.3 GHz processor? Give the result in microseconds (μs).
Suppose we had a processor design with 5 stages where each stage takes the following amount of time: IF: 400 ps ID: 200 ps EX: 300 ps MEM: 500 ps WB: 200 psQ1: If you choose a pipelined design, what is the CPI? Assume that we have enough instructions such that the brief ramp up period at the beginning and the ramp down period at the end with less than 100% utilization does not matter. Q2: If you choose a pipelined design, what is the average execution time per instruction in picoseconds?