Concept explainers
A)
Given Information:
The given code is:
// define structure
square point_color
{
// variable declaration
int c;
int m;
int y;
int k;
};
// declare structure array
struct point_color square[16][16];
int i,j;
// traverse through the array
for(i=0;i<16;i++)
{
//traverse through elements
for(j=0;j<16;j++)
{
//square all elements of the 2-D array
square[j][i].c=0;
square[j][i].m=0;
square[j][i].y=1;
square[j][i].k=0;
}
}
Write hit:
If the information in the cache is reserved or in dirty state then the cache line is updated in its place without updating memory set from its state to dirty.
- If the state of information is in valid state then it executes a write-through operation.
- It then updates the memory and block and changes its blocked state to reserved state.
Write miss:
A partial cache line write is handed as a read miss followed by a write hit. All the other caches are left in the invalid state and the reserved state is occupied by the current state.
B)
Given Information:
The given code is:
// define structure
square point_color
{
// variable declaration
int c;
int m;
int y;
int k;
};
// declare structure array
struct point_color square[16][16];
int i,j;
// traverse through the array
for(i=0;i<16;i++)
{
//traverse through elements
for(j=0;j<16;j++)
{
//square all elements of the 2-D array
square[j][i].c=0;
square[j][i].m=0;
square[j][i].y=1;
square[j][i].k=0;
}
}
Write hit:
If the information in the cache is reserved or in dirty state then the cache line is updated in its place without updating memory set from its state to dirty.
- If the state of information is in valid state then it executes a write-through operation.
- It then updates the memory and block and changes its blocked state to reserved state.
Write miss:
A partial cache line write is handed as a read miss followed by a write hit. All the other caches are left in the invalid state and the reserved state is occupied by the current state.
C)
Given Information:
The given code is:
//define structure
square point_color
{
// variable declaration
int c;
int m;
int y;
int k;
};
// declare structure array
struct point_color square[16][16];
int i,j;
// traverse through the array
for(i=0;i<16;i++)
{
//traverse through elements
for(j=0;j<16;j++)
{
//square all elements of the 2-D array
square[j][i].c=0;
square[j][i].m=0;
square[j][i].y=1;
square[j][i].k=0;
}
}
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Chapter 6 Solutions
Computer Systems: A Programmer's Perspective (3rd Edition)
- Suppose that in 1000 memory references there are 50 misses in the first-level cache, 20 misses in the second-level cache, and 5 misses in the third-level cache. Assume the miss penalty from the L3 cache to memory is 100 clock cycle, the hit time of the L3 cache is 10 clocks, the hit time of the L2 cache is 4 clocks, the hit time of L1 is 1 clock cycle. What is the average memory access time?arrow_forwardFor a direct-mapped cache design with a 32-bit address, the following bitsof the address are used to access the cache. Use the table below. a. What is the cache block size (in words)?b. How many entries does the cache have?c. What is the ration between total bits required for such a cache implementation overthe data storage bit?arrow_forwardFor a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access the cache.Tag Index Offset31–10 9–5 4–01. What is the cache block size (in words)?2. How many entries does the cache have?3. What is the ratio between total bits required for such a cache implementation over the data storage bits?Starting from power on, the following byte-addressed cache references are recorded. Address 0 4 16 132 232 160 1024 30 140 3100 180 2180 How many blocks are replaced? What is the hit ratio? List the fi nal state of the cache, with each valid entry represented as a record of <index, tag, data>arrow_forward
- In the event of an unsatisfied cache request, what should happen to the block being sent to the main memory from the write buffer?arrow_forwardFor a direct-mapped cache design with a 32-bit address, the following bits of the address areused to access the cache.Tag Index Offset31–10 9–6 5–0a– What is the cache block size (in words)? b – How many entries does the cache have? c – What is the ratio between total bits required for such a cache implementation overthe data storage bits?arrow_forwardImagine the difference that exists between a cache that is completely associative and one that is directly mapped.arrow_forward
- What does write back mean in terms of cache? Group of answer choices a. When an error occurs in memory, the cache is written back to the memory. b. When a bit in the cache is changed, the entire block is written to memory. c. When a line is evicted, the block it contains is written to memory.arrow_forwardIn what ways would it be difficult to design a cache replacement method that works with every given address sequence?arrow_forwardDetermines which parts of a log entry will be available to the designated log processing function. Given 64-byte cache blocks and no prefetching, how many cache misses does the following code cause on average for each entry?arrow_forward
- Given the following setup, how many words can be stored in the cache at the same time when the cache is full? A. Direct mapped cache Tag (T) Index (I) Word (W) Byte (B) 17 11 2 2 B. 2-way associative cache Tag (T) Index (I) Word (W) Byte (B) 18 10 2 2 C. 4-way associative cache Tag (T) Index (I) Word (W) Byte (B) 19 9 2 2 D. Fully associative cache Tag (T) Index (I) Word (W) Byte (B) 28 0 2 2arrow_forwardTo what extent does the specified log processing function have access to each field of a log entry? The following code determines the typical number of cache misses per entry while using 64-byte cache blocks and no prefetching.arrow_forwardDraw a line between a cache that is fully associative and one that is directly mapped out.arrow_forward
Systems ArchitectureComputer ScienceISBN:9781305080195Author:Stephen D. BurdPublisher:Cengage Learning