Concept explainers
A)
Given Information:
The given code is:
//variable declaration
//matrix
Int x[2][128];
int i;
//variable to store sum
Int sum=0;
//iterate through the matrix
for(i=0;i<128;i++)
{
//sum of matrix elements
sum+= x[0][i]*x[1][i];
}
Explanation:
- The given array is x[2][128]. The cache is initially empty and it begins to store data from “0x0” addresses.
- Here, size of (int) =4.
- Only memory accesses entries of array “x”.
- C arrays allocated in row-major order which means that each row is in their contiguous memory location.
B)
Given Information:
The given code is:
//variable declaration
//matrix
int x[2][128];
int i;
//variable to store sum
int sum=0;
//iterate through the matrix
for(i=0;i<128;i++)
{
//sum of matrix elements
sum+= x[0][i]*x[1][i];
}
Explanation:
- The given array is x[2][128]. The cache is initially empty and it begins to store data from “0x0” addresses.
- Here, size of (int) =4.
- Only memory accesses entries of array “x”.
- C arrays allocated in row-major order which means that each row is in their contiguous memory location.
C)
Given Information:
The given code is:
//variable declaration
//matrix
Int x[2][128];
int i;
//variable to store sum
Int sum=0;
//iterate through the matrix
for(i=0;i<128;i++)
{
//sum of matrix elements
sum+= x[0][i]*x[1][i];
}
Explanation:
- The given array is x[2][128]. The cache is initially empty and it begins to store data from “0x0” addresses.
- Here, size of (int) =4.
- Only memory accesses entries of array “x”.
- C arrays allocated in row-major order which means that each row is in their contiguous memory location.
D)
Given Information:
The given code is:
//variable declaration
//matrix
int x[2][128];
int i;
//variable to store sum
int sum=0;
//iterate through the matrix
for(i=0;i<128;i++)
{
//sum of matrix elements
sum+= x[0][i]*x[1][i];
}
- The given array is x[2][128]. The cache is initially empty and it begins to store data from “0x0” addresses.
- Here, size of (int) =4.
- Only memory accesses entries of array “x”.
- C arrays allocated in row-major order which means that each row is in their contiguous memory location.
E)
Given Information:
The given code is:
The given code is:
//variable declaration
//matrix
Int x[2][128];
int i;
//variable to store sum
Int sum=0;
//iterate through the matrix
for(i=0;i<128;i++)
{
//sum of matrix elements
sum+= x[0][i]*x[1][i];
}
Explanation:
- The given array is x[2][128]. The cache is initially empty and it begins to store data from “0x0” addresses.
- Here, size of (int) =4.
- Only memory accesses entries of array “x”.
- C arrays allocated in row-major order which means that each row is in their contiguous memory location.
Want to see the full answer?
Check out a sample textbook solutionChapter 6 Solutions
Computer Systems: A Programmer's Perspective (3rd Edition)
- Write a c++ code that implements a program that compares the running time for two loops which access very different number of array elements but which should have roughly the same number of cache misses. Try to estimate the average time for an array access with a cache miss and one without. use the following two loops (in the screenshot provided)arrow_forwardRecall that we have two write policies and write allocation policies, and their combinations can be implemented either in L1 or L2 cache. Assume the following choices for L1 and L2 caches: L1 L2 Write through, non-write allocate Write back, write allocate 1. Buff ers are employed between diff erent levels of memory hierarchy to reduce access latency. For this given confi guration, list the possible buff ers needed between L1 and L2 caches, as well as L2 cache and memory.2. Describe the procedure of handling an L1 write-miss, considering the component involved and the possibility of replacing a dirty block.3. For a multilevel exclusive cache (a block can only reside in one of the L1 and L2 caches), confi guration, describe the procedure of handling an L1 write-miss, considering the component involved and the possibility of replacing a dirty block.Consider the following program and cache behaviors. Data Reads per1000 Instructions Data Writes per1000 Instructions Instruction…arrow_forwardIn layman's terms, here's how dynamic memory allocation works.arrow_forward
- Question no 07: Write C Program Code to simulate Worst-Fit memory management Algorithm for the following Process. Number of Blocks: 6 (B1=6, B2=8, B3=10, B4=15, B5=20, B6=4) Number of Process: 5 (P1=1, P2=12, P3=17, P4=10, P5=6)arrow_forwardTake into account the following scenario: we have a byte-addressable computer with 2-way set associative mapping, 16-bit main memory addresses, and 32 blocks of cache memory. Since there are 8 bytes in a block, you can use that information to calculate how big the offset field has to be.arrow_forwardQ5 Cache Performance Analysis This challenging question tests your understanding of cache. Consider the following C code: int A[16]; int B[16]; int m; ... //A large chunk of code that does NOT access //arrays A and B. ... for (int i=0; i<10; i++) { for (int j=0; j<16; j++) { B[j] = m * A[j] + B[j]; } } Assume this program runs on a 32-bit machine, i.e., the CPU loads/stores 4 bytes from memory in one go. This machine has a 16-bit memory address, and each memory block stores 16 bytes. This machine has a direct-mapped data cache with 16 cache lines. Array A starts at address 0, and B starts at address 256 - both arrays begin at a memory block boundary. Each element of arrays A and B occupies 4 bytes. The values of i, j, and m are stored in CPU registers. What is the total number of data cache misses (including compulsory misses) when running the above code?arrow_forward
- Q5 Cache Performance Analysis This challenging question tests your understanding of cache. Consider the following C code: int A[16]; int B[16]; int m; ... //A large chunk of code that does NOT access //arrays A and B. ... for (int i=0; i<10; i++) { for (int j=0; j<16; j++) { B[j] = m * A[j] + B[j]; } } Assume this program runs on a 32-bit machine, i.e., the CPU loads/stores 4 bytes from memory in one go. This machine has a 16-bit memory address, and each memory block stores 16 bytes. This machine has a direct-mapped data cache with 16 cache lines. Array A starts at address 0, and B starts at address 256 - both arrays begin at a memory block boundary. Each element of arrays A and B occupies 4 bytes. The values of i, j, and m are stored in CPU registers. Assume we change the cache configuration to be 2-way set-associative. This new data cache has 8 sets and 16 bytes per line. The cache uses a Least Recently Used (LRU) replacement policy. How many data cache misses (including…arrow_forwardA computer uses a set-associative cache with 8-blocks per set. How many bits will be used for the counter to apply the (LRU algorithm)? Explain your answer. The following blocks are referenced by the CPU and to be fetched from the RAM to the cache sequentially: (i j k L L j m j n L m j m L k S j P i O k) Assume that the cache set is empty and all the above blocks can be inserted into the set. Use the LRU algorithm to fill in the following table that describes the status of the cache locations for each called block.arrow_forwardQuestion 1 Consider the size of main memory as 32 Bytes and the size of cache memory as 8 Bytes. Implement the Set-Associative mapping technique. Do the following: a) Find the number of bits to address 32 bytes in main memory b) Write the formula to map block of main memory to set of cache memory c) Find the block size, line size, set size, tag size d) Draw the figure to show the distribution of main memory in desired blocks containing bytes e) Draw the figure to show the distribution of cache memory in desired lines containing tag numbers, respective blocks, and byte numbers f) Show the tag allocation for each set (and line) of cache memoryarrow_forward
- The following code, written in C, where elements within the same row are stored contiguously, was implemented on a computer system containing the cache system already discussed.for( i = 0; i < 8; i++ )for( j = 0; j<8000; j++ )a[i][j] = b[i][0] + a[j][i]a) References to which variables exhibit temporal locality?b) References to which variables exhibit spatial locality? (please explain in details)arrow_forward1. Caches are important to providing a high-performance memory hierarchy to processors. Below is a list of 32-bit memory address references, given as word addresses. 42, 137, 66, 50, 38, 225, 173, 22, 19, 88, 51, 43 a. For each of these references, identify the binary address, the tag, and the index given a direct mapped cache with 16 one-word blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty. b. For each of these references, identify the binary address, the tag, and the index given a direct mapped cache with two-word blocks and a total size of 8 blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty. Please explain the process.arrow_forward10. Consider the following code: .386 .model flat, stdcall .stack 4096 ExitProcess PROTO, dwExitCode : DWORD .data aVal SDWORD -6 bVal SWORD 19h cVal DWORD 17h .code mov edx, aVal add edx, edx mov eax, 0FFFFFFFFh mov ax, bVal sub edx, eax Show the content of edx and eax after executing each instruction in Hexadecimaarrow_forward
- Database System ConceptsComputer ScienceISBN:9780078022159Author:Abraham Silberschatz Professor, Henry F. Korth, S. SudarshanPublisher:McGraw-Hill EducationStarting Out with Python (4th Edition)Computer ScienceISBN:9780134444321Author:Tony GaddisPublisher:PEARSONDigital Fundamentals (11th Edition)Computer ScienceISBN:9780132737968Author:Thomas L. FloydPublisher:PEARSON
- C How to Program (8th Edition)Computer ScienceISBN:9780133976892Author:Paul J. Deitel, Harvey DeitelPublisher:PEARSONDatabase Systems: Design, Implementation, & Manag...Computer ScienceISBN:9781337627900Author:Carlos Coronel, Steven MorrisPublisher:Cengage LearningProgrammable Logic ControllersComputer ScienceISBN:9780073373843Author:Frank D. PetruzellaPublisher:McGraw-Hill Education