Computer Systems: A Programmer's Perspective (3rd Edition)
3rd Edition
ISBN: 9780134092669
Author: Bryant, Randal E. Bryant, David R. O'Hallaron, David R., Randal E.; O'Hallaron, Bryant/O'hallaron
Publisher: PEARSON
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Question
Chapter 6, Problem 6.27HW
A)
Program Plan Intro
Given Information:
A 2-way associative cache is given.
For line-0:
| SetIndex | Tag | Valid | Byte0 | Byte1 | Byte2 | Byte3 |
| 0 | 09 | 1 | 86 | 30 | 3F | 10 |
| 1 | 45 | 1 | 60 | 4F | E0 | 23 |
| 2 | EB | 0 | - | - | - | - |
| 3 | 06 | 0 | - | - | - | - |
| 4 | C7 | 1 | 06 | 78 | 07 | C5 |
| 5 | 71 | 1 | 0B | DE | 18 | 4B |
| 6 | 91 | 1 | A0 | B7 | 26 | 2D |
| 7 | 46 | 0 | - | - | - | - |
For line-1:
| SetIndex | Tag | Valid | Byte0 | Byte1 | Byte2 | Byte3 |
| 0 | 00 | 0 | - | - | - | - |
| 1 | 38 | 1 | 00 | BC | 0B | 37 |
| 2 | 0B | 0 | - | - | - | - |
| 3 | 32 | 1 | 12 | 08 | 7B | AD |
| 4 | 05 | 1 | 40 | 67 | C2 | 3B |
| 5 | 6E | 0 | - | - | - | - |
| 6 | F0 | 0 | - | - | - | - |
| 7 | DE | 1 | 12 | C0 | 88 | 37 |
B)
Program Plan Intro
Given Information:
A 2-way associative cache is given.
For line-0:
| SetIndex | Tag | Valid | Byte0 | Byte1 | Byte2 | Byte3 |
| 0 | 09 | 1 | 86 | 30 | 3F | 10 |
| 1 | 45 | 1 | 60 | 4F | E0 | 23 |
| 2 | EB | 0 | - | - | - | - |
| 3 | 06 | 0 | - | - | - | - |
| 4 | C7 | 1 | 06 | 78 | 07 | C5 |
| 5 | 71 | 1 | 0B | DE | 18 | 4B |
| 6 | 91 | 1 | A0 | B7 | 26 | 2D |
| 7 | 46 | 0 | - | - | - | - |
For line-1:
| SetIndex | Tag | Valid | Byte0 | Byte1 | Byte2 | Byte3 |
| 0 | 00 | 0 | - | - | - | - |
| 1 | 38 | 1 | 00 | BC | 0B | 37 |
| 2 | 0B | 0 | - | - | - | - |
| 3 | 32 | 1 | 12 | 08 | 7B | AD |
| 4 | 05 | 1 | 40 | 67 | C2 | 3B |
| 5 | 6E | 0 | - | - | - | - |
| 6 | F0 | 0 | - | - | - | - |
| 7 | DE | 1 | 12 | C0 | 88 | 37 |
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Chapter 6 Solutions
Computer Systems: A Programmer's Perspective (3rd Edition)
Ch. 6.1 - Prob. 6.1PPCh. 6.1 - Prob. 6.2PPCh. 6.1 - Prob. 6.3PPCh. 6.1 - Prob. 6.4PPCh. 6.1 - Prob. 6.5PPCh. 6.1 - Prob. 6.6PPCh. 6.2 - Prob. 6.7PPCh. 6.2 - Prob. 6.8PPCh. 6.4 - Prob. 6.9PPCh. 6.4 - Prob. 6.10PP
Ch. 6.4 - Prob. 6.11PPCh. 6.4 - Prob. 6.12PPCh. 6.4 - Prob. 6.13PPCh. 6.4 - Prob. 6.14PPCh. 6.4 - Prob. 6.15PPCh. 6.4 - Prob. 6.16PPCh. 6.5 - Prob. 6.17PPCh. 6.5 - Prob. 6.18PPCh. 6.5 - Prob. 6.19PPCh. 6.5 - Prob. 6.20PPCh. 6.6 - Prob. 6.21PPCh. 6 - Prob. 6.22HWCh. 6 - Prob. 6.23HWCh. 6 - Suppose that a 2 MB file consisting of 512-byte...Ch. 6 - The following table gives the parameters for a...Ch. 6 - The following table gives the parameters for a...Ch. 6 - Prob. 6.27HWCh. 6 - This problem concerns the cache in Practice...Ch. 6 - Suppose we have a system with the following...Ch. 6 - Suppose we have a system with following...Ch. 6 - Suppose that a program using the cache in Problem...Ch. 6 - Repeat Problem 6.31 for memory address0x16E8 A....Ch. 6 - Prob. 6.33HWCh. 6 - Prob. 6.34HWCh. 6 - Prob. 6.35HWCh. 6 - Prob. 6.36HWCh. 6 - Prob. 6.37HWCh. 6 - Prob. 6.38HWCh. 6 - Prob. 6.39HWCh. 6 - Given the assumptions in Problem 6.38, determine...Ch. 6 - You are writing a new 3D game that you hope will...Ch. 6 - Prob. 6.42HWCh. 6 - Prob. 6.43HWCh. 6 - Prob. 6.45HWCh. 6 - Prob. 6.46HW
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- What obstacles must be surmounted to devise a method for replacing cache that is compatible with any address sequence?arrow_forwardSuppose a computer using direct-mapped cache has 232 (that's 232)232) bytes of byte-addressable main memory, and a cache size of 512 bytes, and each cache block contains 64 bytes. How many blocks of main memory are there? What is the format of a memory address as seen by cache, i.e. what are the sizes of the tag, block, and offset fields? To which cache block will the memory address 0x13A4498A map?arrow_forward3. The table below represents five lines from a cache that uses fully associative mapping with a block size of 8. Identify the address of the shaded data, 0xE6, first in binary and then in hexadecimal. The tag numbers and word id bits are in binary, but the content of the cache (the data) is in hexadecimal. Word id bits Tag 000 001 010 011 100 101 110 111 ------------------------------------------ 1011010 10 65 BA 0F C4 19 6E C3 1100101 21 76 CB 80 D5 2A 7F B5 0011011 32 87 DC 91 E6 3B F0 A6 1100000 43 98 ED A2 F7 4C E1 97 1111100 54 9A FE B3 08 5D D2 88arrow_forward
- Suppose a computer using direct mapped cache has 232 byte of byte-addressable main memory, and a cache of 1024 blocks, where each cache block contains 32 bytes. a) How many blocks of main memory are there? b) What is the format of a memory address as seen by the cache, i.e., what are the sizes of the tag, block, and offset fields? c) To which cache block will the memory address 0x000063FA map?arrow_forwardFor a direct-mapped cache design with a 32-bit address, the following bitsof the address are used to access the cache. Use the table below. a. What is the cache block size (in words)?b. How many entries does the cache have?c. What is the ration between total bits required for such a cache implementation overthe data storage bit?arrow_forwardCan you describe the challenges involved in developing a cache replacement strategy that is compatible with any and all address sequences?arrow_forward
- Imagine the difference that exists between a cache that is completely associative and one that is directly mapped.arrow_forwardConsider a 128-word L2 memory and a 16-word direct mapped L1 cache.a. How many bits are in the address of the L2 memory?b. How many index bits are in the L1 address?c. How many tag bits are in the L1 address?d. How many words from the L2 memory will map to the same word in L1?arrow_forwardFor a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access the cache. We assume that each word has 4 bytes. How many words of data are included in one cache line?arrow_forward
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