Processing stages: The processing of an instruction has number of operations. The operations are organized into particular sequence of stages. It attempts to follow a uniform sequence for all instructions. The description of stages are shown below: Fetch: It uses program counter “PC” as memory address to read instruction bytes from memory. The 4-bit portions “icode” and “ifun” of specifier byte is extracted from instruction. It fetches “valC” that denotes an 8-byte constant. It computes “valP” that denotes value of “PC” plus length of fetched instruction. Decode: The register file is been read with two operands. It gives values “valA” and “valB” for operands. It reads registers with instruction fields “rA” and “rB”. Execute: In this stage the ALU either performs required operation or increments and decrements stack pointer. The resulting value is termed as “valE”. The condition codes are evaluated and destination register is updated based on condition. It determines whether branch should be taken or not in a jump instruction. Memory: The data is been written to memory or read from memory in this stage. The value that is read is determined as “valM”. Write back: The results are been written to register file. It can write up to two results. PC update: The program counter “PC” denotes memory address to read bytes of instruction from memory. It is used to set next instruction’s address. Combinational circuits and HCL expressions: The computational blocks are been constructed by accumulating several logic gates into network. The restrictions are been shown below: Each of input for logic gate should be connected to any one shown below: One of system inputs, that is recognized as primary inputs. Output connection for some element in memory. Output of some logic gate. Outputs obtained from more than two logic gates could not be linked together. The wire would be driven to different voltages. It can cause malfunction in circuit. The network should not have cycles. The loops in circuit can cause ambiguity in function computed by network. The “HCL” denotes a hardware control language that is used for describing control logic of different processor designs.

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Chapter 4, Problem 4.56HW

Program Plan Intro

Processing stages:

The processing of an instruction has number of operations.

The operations are organized into particular sequence of stages.

It attempts to follow a uniform sequence for all instructions.

The description of stages are shown below:

Fetch:

It uses program counter “PC” as memory address to read instruction bytes from memory.

The 4-bit portions “icode” and “ifun” of specifier byte is extracted from instruction.

It fetches “valC” that denotes an 8-byte constant.

It computes “valP” that denotes value of “PC” plus length of fetched instruction.

Decode:

The register file is been read with two operands.

It gives values “valA” and “valB” for operands.

It reads registers with instruction fields “rA” and “rB”.

Execute:

In this stage the ALU either performs required operation or increments and decrements stack pointer.

The resulting value is termed as “valE”.

The condition codes are evaluated and destination register is updated based on condition.

It determines whether branch should be taken or not in a jump instruction.

Memory:

The data is been written to memory or read from memory in this stage.

The value that is read is determined as “valM”.

Write back:

The results are been written to register file.

It can write up to two results.

PC update:

The program counter “PC” denotes memory address to read bytes of instruction from memory.

It is used to set next instruction’s address.

Combinational circuits and HCL expressions:

The computational blocks are been constructed by accumulating several logic gates into network.

The restrictions are been shown below:

Each of input for logic gate should be connected to any one shown below:

One of system inputs, that is recognized as primary inputs.

Output connection for some element in memory.

Output of some logic gate.

Outputs obtained from more than two logic gates could not be linked together.

The wire would be driven to different voltages.

It can cause malfunction in circuit.

The network should not have cycles.

The loops in circuit can cause ambiguity in function computed by network.

The “HCL” denotes a hardware control language that is used for describing control logic of different processor designs.

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