Computer Systems: Program... -Access
3rd Edition
ISBN: 9780134071923
Author: Bryant
Publisher: PEARSON
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Chapter 4.3, Problem 4.24PP
Program Plan Intro
Processing stages:
- The processing of an instruction has number of operations.
- The operations are organized into particular sequence of stages.
- It attempts to follow a uniform sequence for all instructions.
- The description of stages are shown below:
- Fetch:
- It uses program counter “PC” as memory address to read instruction bytes from memory.
- The 4-bit portions “icode” and “ifun” of specifier byte is extracted from instruction.
- It fetches “valC” that denotes an 8-byte constant.
- It computes “valP” that denotes value of “PC” plus length of fetched instruction.
- Decode:
- The register file is been read with two operands.
- It gives values “valA” and “valB” for operands.
- It reads registers with instruction fields “rA” and “rB”.
- Execute:
- In this stage the ALU either performs required operation or increments and decrements stack pointer.
- The resulting value is termed as “valE”.
- The condition codes are evaluated and destination register is updated centered on condition.
- It determines whether branch to be utilized in a jump instruction.
- Memory:
- The memory has data written into it or read operation is done from memory.
- The value that is read is determined as “valM”.
- Write back:
- The results are been written to register file.
- It can write up to 2 results.
- PC update:
- The program counter “PC” denotes memory address to read bytes of instruction from memory.
- It is used to set next instruction’s address.
- Fetch:
Combinational circuits and HCL expressions:
- The computational blocks are been constructed by accumulating several logic gates into network.
- The restrictions are been shown below:
- Each of input for logic gate should be connected to any one shown below:
- One of system inputs, that is identified as primary inputs.
- Output connection for some element in memory.
- Output of some logic gate.
- Outputs obtained from more than two logic gates could not be linked together.
- The wire would be driven to different voltages.
- It can cause malfunction in circuit.
- The network should not contain cycles.
- The loops in circuit can cause ambiguity in function
computed by network.
- The loops in circuit can cause ambiguity in function
- Each of input for logic gate should be connected to any one shown below:
- The “HCL” denotes a hardware control language that is used for describing control logic of different processor designs.
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In this exercise we examine in detail how an instruction is executed in a single-cycle datapath. Problems in this exercise refer to a clock cycle in which theprocessor fetches the following instruction word:
10101100100001010000000000011100
Assume that the data memory is all zeros and that the processor’s registers havethe following values at the beginning of the cycle in which the above instructionword is fetched:
R0
R1
R2
R3
R4
R5
R6
R8
R12
R31
0
2
4
6
13
10
12
16
24
31
a. What are the outputs of the sign-extend and the jump “Shift-Left-2” (near the topof the following Figure) for this instruction word? (Pic3)
b. What are the values of ALU control unit’s inputs (ALUOp and Instruction[5-0])for this instruction? c. What is the new PC address after this instruction is executed? Highlight the paththrough which this value is determined. d. For the ALU and the two add units, what are their data input values?
ALU
Add (PC+4)
Add…
Add control states to the following to implement a two-word load constant value instruction, lv, such that lv $rd,1000000 yields rd=1000000. The constant value being loaded, 1000000 in this case, can be an arbitrary 32-bit value, thus it is the second word of the instruction. The first word of the instruction has the lv opcode and specifies rd. All MIPS instructions are just one word long, so there is no MIPS instruction like this and you will not find an explanation of it in the text, etc. You should use the encoding suggested by the when below, so an instruction like lv $5,42 would be encoded as the two-word sequence op(2)+rd(5), 42.
when (op()) (op(2)) LvStart: PCout, MARin, MEMread, Yin CONST(4), ALUadd, Zin, UNTILmfc MDRout, IRin Zout, PCin, JUMPonop HALT /* Should end here on undecoded op */Lv:
1, Explain how we can find the address location of INT 0AH in Interrupt vector table.
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Chapter 4 Solutions
Computer Systems: Program... -Access
Ch. 4.1 - Prob. 4.1PPCh. 4.1 - Prob. 4.2PPCh. 4.1 - Prob. 4.3PPCh. 4.1 - Prob. 4.4PPCh. 4.1 - Prob. 4.5PPCh. 4.1 - Prob. 4.6PPCh. 4.1 - Prob. 4.7PPCh. 4.1 - Prob. 4.8PPCh. 4.2 - Practice Problem 4.9 (solution page 484) Write an...Ch. 4.2 - Prob. 4.10PP
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